Lines Matching +full:synopsys +full:- +full:dw +full:- +full:mshc +full:- +full:common
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare Multimedia Card Interface driver
14 #include <linux/dma-mapping.h>
39 #include <linux/mmc/slot-gpio.h>
43 /* Common flag combinations */
74 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
79 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
80 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
82 u32 des6; /* Lower 32-bits of Next Descriptor Address */
83 u32 des7; /* Upper 32-bits of Next Descriptor Address */
98 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
111 struct dw_mci_slot *slot = s->private; in dw_mci_req_show()
118 spin_lock_bh(&slot->host->lock); in dw_mci_req_show()
119 mrq = slot->mrq; in dw_mci_req_show()
122 cmd = mrq->cmd; in dw_mci_req_show()
123 data = mrq->data; in dw_mci_req_show()
124 stop = mrq->stop; in dw_mci_req_show()
129 cmd->opcode, cmd->arg, cmd->flags, in dw_mci_req_show()
130 cmd->resp[0], cmd->resp[1], cmd->resp[2], in dw_mci_req_show()
131 cmd->resp[2], cmd->error); in dw_mci_req_show()
134 data->bytes_xfered, data->blocks, in dw_mci_req_show()
135 data->blksz, data->flags, data->error); in dw_mci_req_show()
139 stop->opcode, stop->arg, stop->flags, in dw_mci_req_show()
140 stop->resp[0], stop->resp[1], stop->resp[2], in dw_mci_req_show()
141 stop->resp[2], stop->error); in dw_mci_req_show()
144 spin_unlock_bh(&slot->host->lock); in dw_mci_req_show()
152 struct dw_mci *host = s->private; in dw_mci_regs_show()
154 pm_runtime_get_sync(host->dev); in dw_mci_regs_show()
163 pm_runtime_put_autosuspend(host->dev); in dw_mci_regs_show()
171 struct mmc_host *mmc = slot->mmc; in dw_mci_init_debugfs()
172 struct dw_mci *host = slot->host; in dw_mci_init_debugfs()
175 root = mmc->debugfs_root; in dw_mci_init_debugfs()
181 debugfs_create_u32("state", S_IRUSR, root, &host->state); in dw_mci_init_debugfs()
183 &host->pending_events); in dw_mci_init_debugfs()
185 &host->completed_events); in dw_mci_init_debugfs()
187 fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc); in dw_mci_init_debugfs()
201 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, in dw_mci_ctrl_reset()
204 dev_err(host->dev, in dw_mci_ctrl_reset()
227 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, in dw_mci_wait_while_busy()
231 dev_err(host->dev, "Busy; trying anyway\n"); in dw_mci_wait_while_busy()
237 struct dw_mci *host = slot->host; in mci_send_cmd()
245 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, in mci_send_cmd()
248 dev_err(&slot->mmc->class_dev, in mci_send_cmd()
256 struct dw_mci *host = slot->host; in dw_mci_prepare_command()
259 cmd->error = -EINPROGRESS; in dw_mci_prepare_command()
260 cmdr = cmd->opcode; in dw_mci_prepare_command()
262 if (cmd->opcode == MMC_STOP_TRANSMISSION || in dw_mci_prepare_command()
263 cmd->opcode == MMC_GO_IDLE_STATE || in dw_mci_prepare_command()
264 cmd->opcode == MMC_GO_INACTIVE_STATE || in dw_mci_prepare_command()
265 (cmd->opcode == SD_IO_RW_DIRECT && in dw_mci_prepare_command()
266 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) in dw_mci_prepare_command()
268 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) in dw_mci_prepare_command()
271 if (cmd->opcode == SD_SWITCH_VOLTAGE) { in dw_mci_prepare_command()
278 WARN_ON(slot->host->state != STATE_SENDING_CMD); in dw_mci_prepare_command()
279 slot->host->state = STATE_SENDING_CMD11; in dw_mci_prepare_command()
289 * ever called with a non-zero clock. That shouldn't happen in dw_mci_prepare_command()
293 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); in dw_mci_prepare_command()
299 if (cmd->flags & MMC_RSP_PRESENT) { in dw_mci_prepare_command()
302 if (cmd->flags & MMC_RSP_136) in dw_mci_prepare_command()
306 if (cmd->flags & MMC_RSP_CRC) in dw_mci_prepare_command()
309 if (cmd->data) { in dw_mci_prepare_command()
311 if (cmd->data->flags & MMC_DATA_WRITE) in dw_mci_prepare_command()
315 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) in dw_mci_prepare_command()
326 if (!cmd->data) in dw_mci_prep_stop_abort()
329 stop = &host->stop_abort; in dw_mci_prep_stop_abort()
330 cmdr = cmd->opcode; in dw_mci_prep_stop_abort()
339 stop->opcode = MMC_STOP_TRANSMISSION; in dw_mci_prep_stop_abort()
340 stop->arg = 0; in dw_mci_prep_stop_abort()
341 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; in dw_mci_prep_stop_abort()
343 stop->opcode = SD_IO_RW_DIRECT; in dw_mci_prep_stop_abort()
344 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | in dw_mci_prep_stop_abort()
345 ((cmd->arg >> 28) & 0x7); in dw_mci_prep_stop_abort()
346 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; in dw_mci_prep_stop_abort()
351 cmdr = stop->opcode | SDMMC_CMD_STOP | in dw_mci_prep_stop_abort()
354 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) in dw_mci_prep_stop_abort()
373 host->bus_hz); in dw_mci_set_cto()
391 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_set_cto()
392 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in dw_mci_set_cto()
393 mod_timer(&host->cto_timer, in dw_mci_set_cto()
395 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_set_cto()
401 host->cmd = cmd; in dw_mci_start_command()
402 dev_vdbg(host->dev, in dw_mci_start_command()
404 cmd->arg, cmd_flags); in dw_mci_start_command()
406 mci_writel(host, CMDARG, cmd->arg); in dw_mci_start_command()
419 struct mmc_command *stop = &host->stop_abort; in send_stop_abort()
421 dw_mci_start_command(host, stop, host->stop_cmdr); in send_stop_abort()
427 if (host->using_dma) { in dw_mci_stop_dma()
428 host->dma_ops->stop(host); in dw_mci_stop_dma()
429 host->dma_ops->cleanup(host); in dw_mci_stop_dma()
433 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_stop_dma()
438 struct mmc_data *data = host->data; in dw_mci_dma_cleanup()
440 if (data && data->host_cookie == COOKIE_MAPPED) { in dw_mci_dma_cleanup()
441 dma_unmap_sg(host->dev, in dw_mci_dma_cleanup()
442 data->sg, in dw_mci_dma_cleanup()
443 data->sg_len, in dw_mci_dma_cleanup()
445 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_dma_cleanup()
477 struct mmc_data *data = host->data; in dw_mci_dmac_complete_dma()
479 dev_vdbg(host->dev, "DMA complete\n"); in dw_mci_dmac_complete_dma()
481 if ((host->use_dma == TRANS_MODE_EDMAC) && in dw_mci_dmac_complete_dma()
482 data && (data->flags & MMC_DATA_READ)) in dw_mci_dmac_complete_dma()
484 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), in dw_mci_dmac_complete_dma()
485 data->sg, in dw_mci_dmac_complete_dma()
486 data->sg_len, in dw_mci_dmac_complete_dma()
489 host->dma_ops->cleanup(host); in dw_mci_dmac_complete_dma()
496 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_dmac_complete_dma()
497 tasklet_schedule(&host->tasklet); in dw_mci_dmac_complete_dma()
505 if (host->dma_64bit_address == 1) { in dw_mci_idmac_init()
508 host->ring_size = in dw_mci_idmac_init()
512 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; in dw_mci_idmac_init()
514 p->des6 = (host->sg_dma + in dw_mci_idmac_init()
518 p->des7 = (u64)(host->sg_dma + in dw_mci_idmac_init()
522 p->des0 = 0; in dw_mci_idmac_init()
523 p->des1 = 0; in dw_mci_idmac_init()
524 p->des2 = 0; in dw_mci_idmac_init()
525 p->des3 = 0; in dw_mci_idmac_init()
528 /* Set the last descriptor as the end-of-ring descriptor */ in dw_mci_idmac_init()
529 p->des6 = host->sg_dma & 0xffffffff; in dw_mci_idmac_init()
530 p->des7 = (u64)host->sg_dma >> 32; in dw_mci_idmac_init()
531 p->des0 = IDMAC_DES0_ER; in dw_mci_idmac_init()
536 host->ring_size = in dw_mci_idmac_init()
540 for (i = 0, p = host->sg_cpu; in dw_mci_idmac_init()
541 i < host->ring_size - 1; in dw_mci_idmac_init()
543 p->des3 = cpu_to_le32(host->sg_dma + in dw_mci_idmac_init()
545 p->des0 = 0; in dw_mci_idmac_init()
546 p->des1 = 0; in dw_mci_idmac_init()
549 /* Set the last descriptor as the end-of-ring descriptor */ in dw_mci_idmac_init()
550 p->des3 = cpu_to_le32(host->sg_dma); in dw_mci_idmac_init()
551 p->des0 = cpu_to_le32(IDMAC_DES0_ER); in dw_mci_idmac_init()
556 if (host->dma_64bit_address == 1) { in dw_mci_idmac_init()
557 /* Mask out interrupts - get Tx & Rx complete only */ in dw_mci_idmac_init()
563 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); in dw_mci_idmac_init()
564 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); in dw_mci_idmac_init()
567 /* Mask out interrupts - get Tx & Rx complete only */ in dw_mci_idmac_init()
573 mci_writel(host, DBADDR, host->sg_dma); in dw_mci_idmac_init()
588 desc_first = desc_last = desc = host->sg_cpu; in dw_mci_prepare_desc64()
591 unsigned int length = sg_dma_len(&data->sg[i]); in dw_mci_prepare_desc64()
593 u64 mem_addr = sg_dma_address(&data->sg[i]); in dw_mci_prepare_desc64()
599 length -= desc_len; in dw_mci_prepare_desc64()
607 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc64()
616 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | in dw_mci_prepare_desc64()
623 desc->des4 = mem_addr & 0xffffffff; in dw_mci_prepare_desc64()
624 desc->des5 = mem_addr >> 32; in dw_mci_prepare_desc64()
635 desc_first->des0 |= IDMAC_DES0_FD; in dw_mci_prepare_desc64()
638 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); in dw_mci_prepare_desc64()
639 desc_last->des0 |= IDMAC_DES0_LD; in dw_mci_prepare_desc64()
644 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); in dw_mci_prepare_desc64()
645 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); in dw_mci_prepare_desc64()
647 return -EINVAL; in dw_mci_prepare_desc64()
660 desc_first = desc_last = desc = host->sg_cpu; in dw_mci_prepare_desc32()
663 unsigned int length = sg_dma_len(&data->sg[i]); in dw_mci_prepare_desc32()
665 u32 mem_addr = sg_dma_address(&data->sg[i]); in dw_mci_prepare_desc32()
671 length -= desc_len; in dw_mci_prepare_desc32()
679 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc32()
689 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | in dw_mci_prepare_desc32()
697 desc->des2 = cpu_to_le32(mem_addr); in dw_mci_prepare_desc32()
708 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); in dw_mci_prepare_desc32()
711 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | in dw_mci_prepare_desc32()
713 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); in dw_mci_prepare_desc32()
718 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); in dw_mci_prepare_desc32()
719 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); in dw_mci_prepare_desc32()
721 return -EINVAL; in dw_mci_prepare_desc32()
729 if (host->dma_64bit_address == 1) in dw_mci_idmac_start_dma()
730 ret = dw_mci_prepare_desc64(host, host->data, sg_len); in dw_mci_idmac_start_dma()
732 ret = dw_mci_prepare_desc32(host, host->data, sg_len); in dw_mci_idmac_start_dma()
774 dmaengine_terminate_async(host->dms->ch); in dw_mci_edmac_stop_dma()
782 struct scatterlist *sgl = host->data->sg; in dw_mci_edmac_start_dma()
784 u32 sg_elems = host->data->sg_len; in dw_mci_edmac_start_dma()
786 u32 fifo_offset = host->fifo_reg - host->regs; in dw_mci_edmac_start_dma()
791 cfg.dst_addr = host->phy_regs + fifo_offset; in dw_mci_edmac_start_dma()
801 if (host->data->flags & MMC_DATA_WRITE) in dw_mci_edmac_start_dma()
806 ret = dmaengine_slave_config(host->dms->ch, &cfg); in dw_mci_edmac_start_dma()
808 dev_err(host->dev, "Failed to config edmac.\n"); in dw_mci_edmac_start_dma()
809 return -EBUSY; in dw_mci_edmac_start_dma()
812 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, in dw_mci_edmac_start_dma()
816 dev_err(host->dev, "Can't prepare slave sg.\n"); in dw_mci_edmac_start_dma()
817 return -EBUSY; in dw_mci_edmac_start_dma()
821 desc->callback = dw_mci_dmac_complete_dma; in dw_mci_edmac_start_dma()
822 desc->callback_param = (void *)host; in dw_mci_edmac_start_dma()
826 if (host->data->flags & MMC_DATA_WRITE) in dw_mci_edmac_start_dma()
827 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, in dw_mci_edmac_start_dma()
830 dma_async_issue_pending(host->dms->ch); in dw_mci_edmac_start_dma()
838 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); in dw_mci_edmac_init()
839 if (!host->dms) in dw_mci_edmac_init()
840 return -ENOMEM; in dw_mci_edmac_init()
842 host->dms->ch = dma_request_chan(host->dev, "rx-tx"); in dw_mci_edmac_init()
843 if (IS_ERR(host->dms->ch)) { in dw_mci_edmac_init()
844 int ret = PTR_ERR(host->dms->ch); in dw_mci_edmac_init()
846 dev_err(host->dev, "Failed to get external DMA channel.\n"); in dw_mci_edmac_init()
847 kfree(host->dms); in dw_mci_edmac_init()
848 host->dms = NULL; in dw_mci_edmac_init()
857 if (host->dms) { in dw_mci_edmac_exit()
858 if (host->dms->ch) { in dw_mci_edmac_exit()
859 dma_release_channel(host->dms->ch); in dw_mci_edmac_exit()
860 host->dms->ch = NULL; in dw_mci_edmac_exit()
862 kfree(host->dms); in dw_mci_edmac_exit()
863 host->dms = NULL; in dw_mci_edmac_exit()
883 if (data->host_cookie == COOKIE_PRE_MAPPED) in dw_mci_pre_dma_transfer()
884 return data->sg_len; in dw_mci_pre_dma_transfer()
888 * non-word-aligned buffers or lengths. Also, we don't bother in dw_mci_pre_dma_transfer()
891 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) in dw_mci_pre_dma_transfer()
892 return -EINVAL; in dw_mci_pre_dma_transfer()
894 if (data->blksz & 3) in dw_mci_pre_dma_transfer()
895 return -EINVAL; in dw_mci_pre_dma_transfer()
897 for_each_sg(data->sg, sg, data->sg_len, i) { in dw_mci_pre_dma_transfer()
898 if (sg->offset & 3 || sg->length & 3) in dw_mci_pre_dma_transfer()
899 return -EINVAL; in dw_mci_pre_dma_transfer()
902 sg_len = dma_map_sg(host->dev, in dw_mci_pre_dma_transfer()
903 data->sg, in dw_mci_pre_dma_transfer()
904 data->sg_len, in dw_mci_pre_dma_transfer()
907 return -EINVAL; in dw_mci_pre_dma_transfer()
909 data->host_cookie = cookie; in dw_mci_pre_dma_transfer()
918 struct mmc_data *data = mrq->data; in dw_mci_pre_req()
920 if (!slot->host->use_dma || !data) in dw_mci_pre_req()
924 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_pre_req()
926 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, in dw_mci_pre_req()
928 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_pre_req()
936 struct mmc_data *data = mrq->data; in dw_mci_post_req()
938 if (!slot->host->use_dma || !data) in dw_mci_post_req()
941 if (data->host_cookie != COOKIE_UNMAPPED) in dw_mci_post_req()
942 dma_unmap_sg(slot->host->dev, in dw_mci_post_req()
943 data->sg, in dw_mci_post_req()
944 data->sg_len, in dw_mci_post_req()
946 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_post_req()
953 struct dw_mci *host = slot->host; in dw_mci_get_cd()
957 if (((mmc->caps & MMC_CAP_NEEDS_POLL) in dw_mci_get_cd()
961 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { in dw_mci_get_cd()
962 if (mmc->caps & MMC_CAP_NEEDS_POLL) { in dw_mci_get_cd()
963 dev_info(&mmc->class_dev, in dw_mci_get_cd()
966 dev_info(&mmc->class_dev, in dw_mci_get_cd()
967 "card is non-removable.\n"); in dw_mci_get_cd()
969 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); in dw_mci_get_cd()
976 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) in dw_mci_get_cd()
979 spin_lock_bh(&host->lock); in dw_mci_get_cd()
980 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) in dw_mci_get_cd()
981 dev_dbg(&mmc->class_dev, "card is present\n"); in dw_mci_get_cd()
983 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) in dw_mci_get_cd()
984 dev_dbg(&mmc->class_dev, "card is not present\n"); in dw_mci_get_cd()
985 spin_unlock_bh(&host->lock); in dw_mci_get_cd()
992 unsigned int blksz = data->blksz; in dw_mci_adjust_fifoth()
994 u32 fifo_width = 1 << host->data_shift; in dw_mci_adjust_fifoth()
997 int idx = ARRAY_SIZE(mszs) - 1; in dw_mci_adjust_fifoth()
1000 if (!host->use_dma) in dw_mci_adjust_fifoth()
1003 tx_wmark = (host->fifo_depth) / 2; in dw_mci_adjust_fifoth()
1004 tx_wmark_invers = host->fifo_depth - tx_wmark; in dw_mci_adjust_fifoth()
1017 rx_wmark = mszs[idx] - 1; in dw_mci_adjust_fifoth()
1020 } while (--idx > 0); in dw_mci_adjust_fifoth()
1032 unsigned int blksz = data->blksz; in dw_mci_ctrl_thld()
1041 if (host->verid < DW_MMC_240A || in dw_mci_ctrl_thld()
1042 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) in dw_mci_ctrl_thld()
1049 if (data->flags & MMC_DATA_WRITE && in dw_mci_ctrl_thld()
1050 host->timing != MMC_TIMING_MMC_HS400) in dw_mci_ctrl_thld()
1053 if (data->flags & MMC_DATA_WRITE) in dw_mci_ctrl_thld()
1058 if (host->timing != MMC_TIMING_MMC_HS200 && in dw_mci_ctrl_thld()
1059 host->timing != MMC_TIMING_UHS_SDR104 && in dw_mci_ctrl_thld()
1060 host->timing != MMC_TIMING_MMC_HS400) in dw_mci_ctrl_thld()
1063 blksz_depth = blksz / (1 << host->data_shift); in dw_mci_ctrl_thld()
1064 fifo_depth = host->fifo_depth; in dw_mci_ctrl_thld()
1088 host->using_dma = 0; in dw_mci_submit_data_dma()
1091 if (!host->use_dma) in dw_mci_submit_data_dma()
1092 return -ENODEV; in dw_mci_submit_data_dma()
1096 host->dma_ops->stop(host); in dw_mci_submit_data_dma()
1100 host->using_dma = 1; in dw_mci_submit_data_dma()
1102 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_submit_data_dma()
1103 dev_vdbg(host->dev, in dw_mci_submit_data_dma()
1105 (unsigned long)host->sg_cpu, in dw_mci_submit_data_dma()
1106 (unsigned long)host->sg_dma, in dw_mci_submit_data_dma()
1114 if (host->prev_blksz != data->blksz) in dw_mci_submit_data_dma()
1123 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_submit_data_dma()
1127 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_submit_data_dma()
1129 if (host->dma_ops->start(host, sg_len)) { in dw_mci_submit_data_dma()
1130 host->dma_ops->stop(host); in dw_mci_submit_data_dma()
1132 dev_dbg(host->dev, in dw_mci_submit_data_dma()
1135 return -ENODEV; in dw_mci_submit_data_dma()
1147 data->error = -EINPROGRESS; in dw_mci_submit_data()
1149 WARN_ON(host->data); in dw_mci_submit_data()
1150 host->sg = NULL; in dw_mci_submit_data()
1151 host->data = data; in dw_mci_submit_data()
1153 if (data->flags & MMC_DATA_READ) in dw_mci_submit_data()
1154 host->dir_status = DW_MCI_RECV_STATUS; in dw_mci_submit_data()
1156 host->dir_status = DW_MCI_SEND_STATUS; in dw_mci_submit_data()
1161 if (host->data->flags & MMC_DATA_READ) in dw_mci_submit_data()
1166 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); in dw_mci_submit_data()
1167 host->sg = data->sg; in dw_mci_submit_data()
1168 host->part_buf_start = 0; in dw_mci_submit_data()
1169 host->part_buf_count = 0; in dw_mci_submit_data()
1173 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_submit_data()
1177 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_submit_data()
1189 if (host->wm_aligned) in dw_mci_submit_data()
1192 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_submit_data()
1193 host->prev_blksz = 0; in dw_mci_submit_data()
1200 host->prev_blksz = data->blksz; in dw_mci_submit_data()
1206 struct dw_mci *host = slot->host; in dw_mci_setup_bus()
1207 unsigned int clock = slot->clock; in dw_mci_setup_bus()
1213 if (host->state == STATE_WAITING_CMD11_DONE) in dw_mci_setup_bus()
1216 slot->mmc->actual_clock = 0; in dw_mci_setup_bus()
1221 } else if (clock != host->current_speed || force_clkinit) { in dw_mci_setup_bus()
1222 div = host->bus_hz / clock; in dw_mci_setup_bus()
1223 if (host->bus_hz % clock && host->bus_hz > clock) in dw_mci_setup_bus()
1226 * over-clocking the card. in dw_mci_setup_bus()
1230 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; in dw_mci_setup_bus()
1232 if ((clock != slot->__clk_old && in dw_mci_setup_bus()
1233 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || in dw_mci_setup_bus()
1237 dev_info(&slot->mmc->class_dev, in dw_mci_setup_bus()
1239 slot->id, host->bus_hz, clock, in dw_mci_setup_bus()
1240 div ? ((host->bus_hz / div) >> 1) : in dw_mci_setup_bus()
1241 host->bus_hz, div); in dw_mci_setup_bus()
1247 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && in dw_mci_setup_bus()
1248 slot->mmc->f_min == clock) in dw_mci_setup_bus()
1249 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); in dw_mci_setup_bus()
1266 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; in dw_mci_setup_bus()
1267 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) in dw_mci_setup_bus()
1268 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; in dw_mci_setup_bus()
1275 slot->__clk_old = clock; in dw_mci_setup_bus()
1276 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : in dw_mci_setup_bus()
1277 host->bus_hz; in dw_mci_setup_bus()
1280 host->current_speed = clock; in dw_mci_setup_bus()
1283 mci_writel(host, CTYPE, (slot->ctype << slot->id)); in dw_mci_setup_bus()
1289 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_set_data_timeout()
1293 if (drv_data && drv_data->set_data_timeout) in dw_mci_set_data_timeout()
1294 return drv_data->set_data_timeout(host, timeout_ns); in dw_mci_set_data_timeout()
1300 tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC); in dw_mci_set_data_timeout()
1313 dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x", in dw_mci_set_data_timeout()
1325 mrq = slot->mrq; in __dw_mci_start_request()
1327 host->mrq = mrq; in __dw_mci_start_request()
1329 host->pending_events = 0; in __dw_mci_start_request()
1330 host->completed_events = 0; in __dw_mci_start_request()
1331 host->cmd_status = 0; in __dw_mci_start_request()
1332 host->data_status = 0; in __dw_mci_start_request()
1333 host->dir_status = 0; in __dw_mci_start_request()
1335 data = cmd->data; in __dw_mci_start_request()
1337 dw_mci_set_data_timeout(host, data->timeout_ns); in __dw_mci_start_request()
1338 mci_writel(host, BYTCNT, data->blksz*data->blocks); in __dw_mci_start_request()
1339 mci_writel(host, BLKSIZ, data->blksz); in __dw_mci_start_request()
1342 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); in __dw_mci_start_request()
1345 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) in __dw_mci_start_request()
1355 if (cmd->opcode == SD_SWITCH_VOLTAGE) { in __dw_mci_start_request()
1368 spin_lock_irqsave(&host->irq_lock, irqflags); in __dw_mci_start_request()
1369 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in __dw_mci_start_request()
1370 mod_timer(&host->cmd11_timer, in __dw_mci_start_request()
1372 spin_unlock_irqrestore(&host->irq_lock, irqflags); in __dw_mci_start_request()
1375 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); in __dw_mci_start_request()
1381 struct mmc_request *mrq = slot->mrq; in dw_mci_start_request()
1384 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; in dw_mci_start_request()
1388 /* must be called with host->lock held */
1392 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", in dw_mci_queue_request()
1393 host->state); in dw_mci_queue_request()
1395 slot->mrq = mrq; in dw_mci_queue_request()
1397 if (host->state == STATE_WAITING_CMD11_DONE) { in dw_mci_queue_request()
1398 dev_warn(&slot->mmc->class_dev, in dw_mci_queue_request()
1405 host->state = STATE_IDLE; in dw_mci_queue_request()
1408 if (host->state == STATE_IDLE) { in dw_mci_queue_request()
1409 host->state = STATE_SENDING_CMD; in dw_mci_queue_request()
1412 list_add_tail(&slot->queue_node, &host->queue); in dw_mci_queue_request()
1419 struct dw_mci *host = slot->host; in dw_mci_request()
1421 WARN_ON(slot->mrq); in dw_mci_request()
1430 mrq->cmd->error = -ENOMEDIUM; in dw_mci_request()
1435 spin_lock_bh(&host->lock); in dw_mci_request()
1439 spin_unlock_bh(&host->lock); in dw_mci_request()
1445 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; in dw_mci_set_ios()
1449 switch (ios->bus_width) { in dw_mci_set_ios()
1451 slot->ctype = SDMMC_CTYPE_4BIT; in dw_mci_set_ios()
1454 slot->ctype = SDMMC_CTYPE_8BIT; in dw_mci_set_ios()
1458 slot->ctype = SDMMC_CTYPE_1BIT; in dw_mci_set_ios()
1461 regs = mci_readl(slot->host, UHS_REG); in dw_mci_set_ios()
1464 if (ios->timing == MMC_TIMING_MMC_DDR52 || in dw_mci_set_ios()
1465 ios->timing == MMC_TIMING_UHS_DDR50 || in dw_mci_set_ios()
1466 ios->timing == MMC_TIMING_MMC_HS400) in dw_mci_set_ios()
1467 regs |= ((0x1 << slot->id) << 16); in dw_mci_set_ios()
1469 regs &= ~((0x1 << slot->id) << 16); in dw_mci_set_ios()
1471 mci_writel(slot->host, UHS_REG, regs); in dw_mci_set_ios()
1472 slot->host->timing = ios->timing; in dw_mci_set_ios()
1475 * Use mirror of ios->clock to prevent race with mmc in dw_mci_set_ios()
1478 slot->clock = ios->clock; in dw_mci_set_ios()
1480 if (drv_data && drv_data->set_ios) in dw_mci_set_ios()
1481 drv_data->set_ios(slot->host, ios); in dw_mci_set_ios()
1483 switch (ios->power_mode) { in dw_mci_set_ios()
1485 if (!IS_ERR(mmc->supply.vmmc)) { in dw_mci_set_ios()
1486 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in dw_mci_set_ios()
1487 ios->vdd); in dw_mci_set_ios()
1489 dev_err(slot->host->dev, in dw_mci_set_ios()
1495 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); in dw_mci_set_ios()
1496 regs = mci_readl(slot->host, PWREN); in dw_mci_set_ios()
1497 regs |= (1 << slot->id); in dw_mci_set_ios()
1498 mci_writel(slot->host, PWREN, regs); in dw_mci_set_ios()
1501 if (!slot->host->vqmmc_enabled) { in dw_mci_set_ios()
1502 if (!IS_ERR(mmc->supply.vqmmc)) { in dw_mci_set_ios()
1503 ret = regulator_enable(mmc->supply.vqmmc); in dw_mci_set_ios()
1505 dev_err(slot->host->dev, in dw_mci_set_ios()
1508 slot->host->vqmmc_enabled = true; in dw_mci_set_ios()
1512 slot->host->vqmmc_enabled = true; in dw_mci_set_ios()
1516 dw_mci_ctrl_reset(slot->host, in dw_mci_set_ios()
1528 if (!IS_ERR(mmc->supply.vmmc)) in dw_mci_set_ios()
1529 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in dw_mci_set_ios()
1531 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) in dw_mci_set_ios()
1532 regulator_disable(mmc->supply.vqmmc); in dw_mci_set_ios()
1533 slot->host->vqmmc_enabled = false; in dw_mci_set_ios()
1535 regs = mci_readl(slot->host, PWREN); in dw_mci_set_ios()
1536 regs &= ~(1 << slot->id); in dw_mci_set_ios()
1537 mci_writel(slot->host, PWREN, regs); in dw_mci_set_ios()
1543 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) in dw_mci_set_ios()
1544 slot->host->state = STATE_IDLE; in dw_mci_set_ios()
1556 status = mci_readl(slot->host, STATUS); in dw_mci_card_busy()
1564 struct dw_mci *host = slot->host; in dw_mci_switch_voltage()
1565 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_switch_voltage()
1567 u32 v18 = SDMMC_UHS_18V << slot->id; in dw_mci_switch_voltage()
1570 if (drv_data && drv_data->switch_voltage) in dw_mci_switch_voltage()
1571 return drv_data->switch_voltage(mmc, ios); in dw_mci_switch_voltage()
1579 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) in dw_mci_switch_voltage()
1584 if (!IS_ERR(mmc->supply.vqmmc)) { in dw_mci_switch_voltage()
1587 dev_dbg(&mmc->class_dev, in dw_mci_switch_voltage()
1588 "Regulator set error %d - %s V\n", in dw_mci_switch_voltage()
1609 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; in dw_mci_get_ro()
1611 dev_dbg(&mmc->class_dev, "card is %s\n", in dw_mci_get_ro()
1612 read_only ? "read-only" : "read-write"); in dw_mci_get_ro()
1620 struct dw_mci *host = slot->host; in dw_mci_hw_reset()
1623 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_hw_reset()
1637 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); in dw_mci_hw_reset()
1640 reset |= SDMMC_RST_HWACTIVE << slot->id; in dw_mci_hw_reset()
1647 struct dw_mci *host = slot->host; in dw_mci_prepare_sdio_irq()
1648 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; in dw_mci_prepare_sdio_irq()
1660 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); in dw_mci_prepare_sdio_irq()
1663 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); in dw_mci_prepare_sdio_irq()
1676 struct dw_mci *host = slot->host; in __dw_mci_enable_sdio_irq()
1680 spin_lock_irqsave(&host->irq_lock, irqflags); in __dw_mci_enable_sdio_irq()
1685 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); in __dw_mci_enable_sdio_irq()
1687 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); in __dw_mci_enable_sdio_irq()
1690 spin_unlock_irqrestore(&host->irq_lock, irqflags); in __dw_mci_enable_sdio_irq()
1696 struct dw_mci *host = slot->host; in dw_mci_enable_sdio_irq()
1703 pm_runtime_get_noresume(host->dev); in dw_mci_enable_sdio_irq()
1705 pm_runtime_put_noidle(host->dev); in dw_mci_enable_sdio_irq()
1718 struct dw_mci *host = slot->host; in dw_mci_execute_tuning()
1719 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_execute_tuning()
1720 int err = -EINVAL; in dw_mci_execute_tuning()
1722 if (drv_data && drv_data->execute_tuning) in dw_mci_execute_tuning()
1723 err = drv_data->execute_tuning(slot, opcode); in dw_mci_execute_tuning()
1731 struct dw_mci *host = slot->host; in dw_mci_prepare_hs400_tuning()
1732 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_prepare_hs400_tuning()
1734 if (drv_data && drv_data->prepare_hs400_tuning) in dw_mci_prepare_hs400_tuning()
1735 return drv_data->prepare_hs400_tuning(host, ios); in dw_mci_prepare_hs400_tuning()
1748 * the scatter-gather pointer to NULL. in dw_mci_reset()
1750 if (host->sg) { in dw_mci_reset()
1751 sg_miter_stop(&host->sg_miter); in dw_mci_reset()
1752 host->sg = NULL; in dw_mci_reset()
1755 if (host->use_dma) in dw_mci_reset()
1765 if (!host->use_dma) { in dw_mci_reset()
1771 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, in dw_mci_reset()
1775 dev_err(host->dev, in dw_mci_reset()
1787 dev_err(host->dev, in dw_mci_reset()
1794 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_reset()
1802 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); in dw_mci_reset()
1829 spin_lock_irqsave(&host->irq_lock, flags); in dw_mci_fault_timer()
1835 if (!host->data_status) { in dw_mci_fault_timer()
1836 host->data_status = SDMMC_INT_DCRC; in dw_mci_fault_timer()
1837 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_fault_timer()
1838 tasklet_schedule(&host->tasklet); in dw_mci_fault_timer()
1841 spin_unlock_irqrestore(&host->irq_lock, flags); in dw_mci_fault_timer()
1848 struct mmc_data *data = host->data; in dw_mci_start_fault_timer()
1850 if (!data || data->blocks <= 1) in dw_mci_start_fault_timer()
1853 if (!should_fail(&host->fail_data_crc, 1)) in dw_mci_start_fault_timer()
1859 hrtimer_start(&host->fault_timer, in dw_mci_start_fault_timer()
1866 hrtimer_cancel(&host->fault_timer); in dw_mci_stop_fault_timer()
1871 host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER; in dw_mci_init_fault()
1873 hrtimer_init(&host->fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in dw_mci_init_fault()
1874 host->fault_timer.function = dw_mci_fault_timer; in dw_mci_init_fault()
1891 __releases(&host->lock) in dw_mci_request_end()
1892 __acquires(&host->lock) in dw_mci_request_end()
1895 struct mmc_host *prev_mmc = host->slot->mmc; in dw_mci_request_end()
1897 WARN_ON(host->cmd || host->data); in dw_mci_request_end()
1899 host->slot->mrq = NULL; in dw_mci_request_end()
1900 host->mrq = NULL; in dw_mci_request_end()
1901 if (!list_empty(&host->queue)) { in dw_mci_request_end()
1902 slot = list_entry(host->queue.next, in dw_mci_request_end()
1904 list_del(&slot->queue_node); in dw_mci_request_end()
1905 dev_vdbg(host->dev, "list not empty: %s is next\n", in dw_mci_request_end()
1906 mmc_hostname(slot->mmc)); in dw_mci_request_end()
1907 host->state = STATE_SENDING_CMD; in dw_mci_request_end()
1910 dev_vdbg(host->dev, "list empty\n"); in dw_mci_request_end()
1912 if (host->state == STATE_SENDING_CMD11) in dw_mci_request_end()
1913 host->state = STATE_WAITING_CMD11_DONE; in dw_mci_request_end()
1915 host->state = STATE_IDLE; in dw_mci_request_end()
1918 spin_unlock(&host->lock); in dw_mci_request_end()
1920 spin_lock(&host->lock); in dw_mci_request_end()
1925 u32 status = host->cmd_status; in dw_mci_command_complete()
1927 host->cmd_status = 0; in dw_mci_command_complete()
1930 if (cmd->flags & MMC_RSP_PRESENT) { in dw_mci_command_complete()
1931 if (cmd->flags & MMC_RSP_136) { in dw_mci_command_complete()
1932 cmd->resp[3] = mci_readl(host, RESP0); in dw_mci_command_complete()
1933 cmd->resp[2] = mci_readl(host, RESP1); in dw_mci_command_complete()
1934 cmd->resp[1] = mci_readl(host, RESP2); in dw_mci_command_complete()
1935 cmd->resp[0] = mci_readl(host, RESP3); in dw_mci_command_complete()
1937 cmd->resp[0] = mci_readl(host, RESP0); in dw_mci_command_complete()
1938 cmd->resp[1] = 0; in dw_mci_command_complete()
1939 cmd->resp[2] = 0; in dw_mci_command_complete()
1940 cmd->resp[3] = 0; in dw_mci_command_complete()
1945 cmd->error = -ETIMEDOUT; in dw_mci_command_complete()
1946 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) in dw_mci_command_complete()
1947 cmd->error = -EILSEQ; in dw_mci_command_complete()
1949 cmd->error = -EIO; in dw_mci_command_complete()
1951 cmd->error = 0; in dw_mci_command_complete()
1953 return cmd->error; in dw_mci_command_complete()
1958 u32 status = host->data_status; in dw_mci_data_complete()
1962 data->error = -ETIMEDOUT; in dw_mci_data_complete()
1964 data->error = -EILSEQ; in dw_mci_data_complete()
1966 if (host->dir_status == in dw_mci_data_complete()
1973 data->bytes_xfered = 0; in dw_mci_data_complete()
1974 data->error = -ETIMEDOUT; in dw_mci_data_complete()
1975 } else if (host->dir_status == in dw_mci_data_complete()
1977 data->error = -EILSEQ; in dw_mci_data_complete()
1981 data->error = -EILSEQ; in dw_mci_data_complete()
1984 dev_dbg(host->dev, "data error, status 0x%08x\n", status); in dw_mci_data_complete()
1992 data->bytes_xfered = data->blocks * data->blksz; in dw_mci_data_complete()
1993 data->error = 0; in dw_mci_data_complete()
1996 return data->error; in dw_mci_data_complete()
2001 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_set_drto()
2007 if (drv_data && drv_data->get_drto_clks) in dw_mci_set_drto()
2008 drto_clks = drv_data->get_drto_clks(host); in dw_mci_set_drto()
2016 host->bus_hz); in dw_mci_set_drto()
2018 dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); in dw_mci_set_drto()
2023 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_set_drto()
2024 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) in dw_mci_set_drto()
2025 mod_timer(&host->dto_timer, in dw_mci_set_drto()
2027 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_set_drto()
2032 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in dw_mci_clear_pending_cmd_complete()
2042 WARN_ON(del_timer_sync(&host->cto_timer)); in dw_mci_clear_pending_cmd_complete()
2043 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_clear_pending_cmd_complete()
2050 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) in dw_mci_clear_pending_data_complete()
2054 WARN_ON(del_timer_sync(&host->dto_timer)); in dw_mci_clear_pending_data_complete()
2055 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_clear_pending_data_complete()
2070 spin_lock(&host->lock); in dw_mci_tasklet_func()
2072 state = host->state; in dw_mci_tasklet_func()
2073 data = host->data; in dw_mci_tasklet_func()
2074 mrq = host->mrq; in dw_mci_tasklet_func()
2089 cmd = host->cmd; in dw_mci_tasklet_func()
2090 host->cmd = NULL; in dw_mci_tasklet_func()
2091 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); in dw_mci_tasklet_func()
2093 if (cmd == mrq->sbc && !err) { in dw_mci_tasklet_func()
2094 __dw_mci_start_request(host, host->slot, in dw_mci_tasklet_func()
2095 mrq->cmd); in dw_mci_tasklet_func()
2099 if (cmd->data && err) { in dw_mci_tasklet_func()
2121 if (err != -ETIMEDOUT && in dw_mci_tasklet_func()
2122 host->dir_status == DW_MCI_RECV_STATUS) { in dw_mci_tasklet_func()
2133 if (!cmd->data || err) { in dw_mci_tasklet_func()
2151 &host->pending_events)) { in dw_mci_tasklet_func()
2152 if (!(host->data_status & (SDMMC_INT_DRTO | in dw_mci_tasklet_func()
2161 &host->pending_events)) { in dw_mci_tasklet_func()
2163 * If all data-related interrupts don't come in dw_mci_tasklet_func()
2166 if (host->dir_status == DW_MCI_RECV_STATUS) in dw_mci_tasklet_func()
2171 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); in dw_mci_tasklet_func()
2187 &host->pending_events)) { in dw_mci_tasklet_func()
2188 if (!(host->data_status & (SDMMC_INT_DRTO | in dw_mci_tasklet_func()
2206 if (host->dir_status == DW_MCI_RECV_STATUS) in dw_mci_tasklet_func()
2212 host->data = NULL; in dw_mci_tasklet_func()
2213 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); in dw_mci_tasklet_func()
2217 if (!data->stop || mrq->sbc) { in dw_mci_tasklet_func()
2218 if (mrq->sbc && data->stop) in dw_mci_tasklet_func()
2219 data->stop->error = 0; in dw_mci_tasklet_func()
2224 /* stop command for open-ended transfer*/ in dw_mci_tasklet_func()
2225 if (data->stop) in dw_mci_tasklet_func()
2238 &host->pending_events)) { in dw_mci_tasklet_func()
2239 host->cmd = NULL; in dw_mci_tasklet_func()
2246 * If err has non-zero, in dw_mci_tasklet_func()
2247 * stop-abort command has been already issued. in dw_mci_tasklet_func()
2258 if (mrq->cmd->error && mrq->data) in dw_mci_tasklet_func()
2262 host->cmd = NULL; in dw_mci_tasklet_func()
2263 host->data = NULL; in dw_mci_tasklet_func()
2265 if (!mrq->sbc && mrq->stop) in dw_mci_tasklet_func()
2266 dw_mci_command_complete(host, mrq->stop); in dw_mci_tasklet_func()
2268 host->cmd_status = 0; in dw_mci_tasklet_func()
2275 &host->pending_events)) in dw_mci_tasklet_func()
2283 host->state = state; in dw_mci_tasklet_func()
2285 spin_unlock(&host->lock); in dw_mci_tasklet_func()
2292 memcpy((void *)&host->part_buf, buf, cnt); in dw_mci_set_part_bytes()
2293 host->part_buf_count = cnt; in dw_mci_set_part_bytes()
2299 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); in dw_mci_push_part_bytes()
2300 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); in dw_mci_push_part_bytes()
2301 host->part_buf_count += cnt; in dw_mci_push_part_bytes()
2308 cnt = min_t(int, cnt, host->part_buf_count); in dw_mci_pull_part_bytes()
2310 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, in dw_mci_pull_part_bytes()
2312 host->part_buf_count -= cnt; in dw_mci_pull_part_bytes()
2313 host->part_buf_start += cnt; in dw_mci_pull_part_bytes()
2321 memcpy(buf, &host->part_buf, cnt); in dw_mci_pull_final_bytes()
2322 host->part_buf_start = cnt; in dw_mci_pull_final_bytes()
2323 host->part_buf_count = (1 << host->data_shift) - cnt; in dw_mci_pull_final_bytes()
2328 struct mmc_data *data = host->data; in dw_mci_push_data16()
2332 if (unlikely(host->part_buf_count)) { in dw_mci_push_data16()
2336 cnt -= len; in dw_mci_push_data16()
2337 if (host->part_buf_count == 2) { in dw_mci_push_data16()
2338 mci_fifo_writew(host->fifo_reg, host->part_buf16); in dw_mci_push_data16()
2339 host->part_buf_count = 0; in dw_mci_push_data16()
2346 int len = min(cnt & -2, (int)sizeof(aligned_buf)); in dw_mci_push_data16()
2352 cnt -= len; in dw_mci_push_data16()
2355 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data16()
2362 for (; cnt >= 2; cnt -= 2) in dw_mci_push_data16()
2363 mci_fifo_writew(host->fifo_reg, *pdata++); in dw_mci_push_data16()
2370 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data16()
2371 (data->blksz * data->blocks)) in dw_mci_push_data16()
2372 mci_fifo_writew(host->fifo_reg, host->part_buf16); in dw_mci_push_data16()
2383 int len = min(cnt & -2, (int)sizeof(aligned_buf)); in dw_mci_pull_data16()
2388 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2392 cnt -= len; in dw_mci_pull_data16()
2399 for (; cnt >= 2; cnt -= 2) in dw_mci_pull_data16()
2400 *pdata++ = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2404 host->part_buf16 = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2411 struct mmc_data *data = host->data; in dw_mci_push_data32()
2415 if (unlikely(host->part_buf_count)) { in dw_mci_push_data32()
2419 cnt -= len; in dw_mci_push_data32()
2420 if (host->part_buf_count == 4) { in dw_mci_push_data32()
2421 mci_fifo_writel(host->fifo_reg, host->part_buf32); in dw_mci_push_data32()
2422 host->part_buf_count = 0; in dw_mci_push_data32()
2429 int len = min(cnt & -4, (int)sizeof(aligned_buf)); in dw_mci_push_data32()
2435 cnt -= len; in dw_mci_push_data32()
2438 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data32()
2445 for (; cnt >= 4; cnt -= 4) in dw_mci_push_data32()
2446 mci_fifo_writel(host->fifo_reg, *pdata++); in dw_mci_push_data32()
2453 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data32()
2454 (data->blksz * data->blocks)) in dw_mci_push_data32()
2455 mci_fifo_writel(host->fifo_reg, host->part_buf32); in dw_mci_push_data32()
2466 int len = min(cnt & -4, (int)sizeof(aligned_buf)); in dw_mci_pull_data32()
2471 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2475 cnt -= len; in dw_mci_pull_data32()
2482 for (; cnt >= 4; cnt -= 4) in dw_mci_pull_data32()
2483 *pdata++ = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2487 host->part_buf32 = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2494 struct mmc_data *data = host->data; in dw_mci_push_data64()
2498 if (unlikely(host->part_buf_count)) { in dw_mci_push_data64()
2502 cnt -= len; in dw_mci_push_data64()
2504 if (host->part_buf_count == 8) { in dw_mci_push_data64()
2505 mci_fifo_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64()
2506 host->part_buf_count = 0; in dw_mci_push_data64()
2513 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_push_data64()
2519 cnt -= len; in dw_mci_push_data64()
2522 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data64()
2529 for (; cnt >= 8; cnt -= 8) in dw_mci_push_data64()
2530 mci_fifo_writeq(host->fifo_reg, *pdata++); in dw_mci_push_data64()
2537 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data64()
2538 (data->blksz * data->blocks)) in dw_mci_push_data64()
2539 mci_fifo_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64()
2550 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_pull_data64()
2555 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2560 cnt -= len; in dw_mci_pull_data64()
2567 for (; cnt >= 8; cnt -= 8) in dw_mci_pull_data64()
2568 *pdata++ = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2572 host->part_buf = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2586 cnt -= len; in dw_mci_pull_data()
2589 host->pull_data(host, buf, cnt); in dw_mci_pull_data()
2594 struct sg_mapping_iter *sg_miter = &host->sg_miter; in dw_mci_read_data_pio()
2597 struct mmc_data *data = host->data; in dw_mci_read_data_pio()
2598 int shift = host->data_shift; in dw_mci_read_data_pio()
2607 host->sg = sg_miter->piter.sg; in dw_mci_read_data_pio()
2608 buf = sg_miter->addr; in dw_mci_read_data_pio()
2609 remain = sg_miter->length; in dw_mci_read_data_pio()
2614 << shift) + host->part_buf_count; in dw_mci_read_data_pio()
2619 data->bytes_xfered += len; in dw_mci_read_data_pio()
2621 remain -= len; in dw_mci_read_data_pio()
2624 sg_miter->consumed = offset; in dw_mci_read_data_pio()
2634 sg_miter->consumed = 0; in dw_mci_read_data_pio()
2641 host->sg = NULL; in dw_mci_read_data_pio()
2643 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_read_data_pio()
2648 struct sg_mapping_iter *sg_miter = &host->sg_miter; in dw_mci_write_data_pio()
2651 struct mmc_data *data = host->data; in dw_mci_write_data_pio()
2652 int shift = host->data_shift; in dw_mci_write_data_pio()
2655 unsigned int fifo_depth = host->fifo_depth; in dw_mci_write_data_pio()
2662 host->sg = sg_miter->piter.sg; in dw_mci_write_data_pio()
2663 buf = sg_miter->addr; in dw_mci_write_data_pio()
2664 remain = sg_miter->length; in dw_mci_write_data_pio()
2668 fcnt = ((fifo_depth - in dw_mci_write_data_pio()
2670 << shift) - host->part_buf_count; in dw_mci_write_data_pio()
2674 host->push_data(host, (void *)(buf + offset), len); in dw_mci_write_data_pio()
2675 data->bytes_xfered += len; in dw_mci_write_data_pio()
2677 remain -= len; in dw_mci_write_data_pio()
2680 sg_miter->consumed = offset; in dw_mci_write_data_pio()
2688 sg_miter->consumed = 0; in dw_mci_write_data_pio()
2695 host->sg = NULL; in dw_mci_write_data_pio()
2697 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_write_data_pio()
2702 del_timer(&host->cto_timer); in dw_mci_cmd_interrupt()
2704 if (!host->cmd_status) in dw_mci_cmd_interrupt()
2705 host->cmd_status = status; in dw_mci_cmd_interrupt()
2709 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cmd_interrupt()
2710 tasklet_schedule(&host->tasklet); in dw_mci_cmd_interrupt()
2717 struct dw_mci_slot *slot = host->slot; in dw_mci_handle_cd()
2719 mmc_detect_change(slot->mmc, in dw_mci_handle_cd()
2720 msecs_to_jiffies(host->pdata->detect_delay_ms)); in dw_mci_handle_cd()
2727 struct dw_mci_slot *slot = host->slot; in dw_mci_interrupt()
2729 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_interrupt()
2733 if ((host->state == STATE_SENDING_CMD11) && in dw_mci_interrupt()
2742 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2744 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2746 del_timer(&host->cmd11_timer); in dw_mci_interrupt()
2750 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2752 del_timer(&host->cto_timer); in dw_mci_interrupt()
2754 host->cmd_status = pending; in dw_mci_interrupt()
2756 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_interrupt()
2758 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2762 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2764 if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) in dw_mci_interrupt()
2765 del_timer(&host->dto_timer); in dw_mci_interrupt()
2769 host->data_status = pending; in dw_mci_interrupt()
2771 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_interrupt()
2773 if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) in dw_mci_interrupt()
2776 &host->pending_events); in dw_mci_interrupt()
2778 tasklet_schedule(&host->tasklet); in dw_mci_interrupt()
2780 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2784 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2786 del_timer(&host->dto_timer); in dw_mci_interrupt()
2789 if (!host->data_status) in dw_mci_interrupt()
2790 host->data_status = pending; in dw_mci_interrupt()
2792 if (host->dir_status == DW_MCI_RECV_STATUS) { in dw_mci_interrupt()
2793 if (host->sg != NULL) in dw_mci_interrupt()
2796 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_interrupt()
2797 tasklet_schedule(&host->tasklet); in dw_mci_interrupt()
2799 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2804 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) in dw_mci_interrupt()
2810 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) in dw_mci_interrupt()
2815 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2820 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2828 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { in dw_mci_interrupt()
2830 SDMMC_INT_SDIO(slot->sdio_id)); in dw_mci_interrupt()
2832 sdio_signal_irq(slot->mmc); in dw_mci_interrupt()
2837 if (host->use_dma != TRANS_MODE_IDMAC) in dw_mci_interrupt()
2841 if (host->dma_64bit_address == 1) { in dw_mci_interrupt()
2847 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) in dw_mci_interrupt()
2848 host->dma_ops->complete((void *)host); in dw_mci_interrupt()
2856 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) in dw_mci_interrupt()
2857 host->dma_ops->complete((void *)host); in dw_mci_interrupt()
2866 struct dw_mci *host = slot->host; in dw_mci_init_slot_caps()
2867 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_init_slot_caps()
2868 struct mmc_host *mmc = slot->mmc; in dw_mci_init_slot_caps()
2871 if (host->pdata->caps) in dw_mci_init_slot_caps()
2872 mmc->caps = host->pdata->caps; in dw_mci_init_slot_caps()
2874 if (host->pdata->pm_caps) in dw_mci_init_slot_caps()
2875 mmc->pm_caps = host->pdata->pm_caps; in dw_mci_init_slot_caps()
2878 mmc->caps |= drv_data->common_caps; in dw_mci_init_slot_caps()
2880 if (host->dev->of_node) { in dw_mci_init_slot_caps()
2881 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); in dw_mci_init_slot_caps()
2885 ctrl_id = to_platform_device(host->dev)->id; in dw_mci_init_slot_caps()
2888 if (drv_data && drv_data->caps) { in dw_mci_init_slot_caps()
2889 if (ctrl_id >= drv_data->num_caps) { in dw_mci_init_slot_caps()
2890 dev_err(host->dev, "invalid controller id %d\n", in dw_mci_init_slot_caps()
2892 return -EINVAL; in dw_mci_init_slot_caps()
2894 mmc->caps |= drv_data->caps[ctrl_id]; in dw_mci_init_slot_caps()
2897 if (host->pdata->caps2) in dw_mci_init_slot_caps()
2898 mmc->caps2 = host->pdata->caps2; in dw_mci_init_slot_caps()
2901 if (host->minimum_speed) in dw_mci_init_slot_caps()
2902 mmc->f_min = host->minimum_speed; in dw_mci_init_slot_caps()
2904 mmc->f_min = DW_MCI_FREQ_MIN; in dw_mci_init_slot_caps()
2906 if (!mmc->f_max) in dw_mci_init_slot_caps()
2907 mmc->f_max = DW_MCI_FREQ_MAX; in dw_mci_init_slot_caps()
2910 if (mmc->caps & MMC_CAP_SDIO_IRQ) in dw_mci_init_slot_caps()
2911 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in dw_mci_init_slot_caps()
2922 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); in dw_mci_init_slot()
2924 return -ENOMEM; in dw_mci_init_slot()
2927 slot->id = 0; in dw_mci_init_slot()
2928 slot->sdio_id = host->sdio_id0 + slot->id; in dw_mci_init_slot()
2929 slot->mmc = mmc; in dw_mci_init_slot()
2930 slot->host = host; in dw_mci_init_slot()
2931 host->slot = slot; in dw_mci_init_slot()
2933 mmc->ops = &dw_mci_ops; in dw_mci_init_slot()
2940 if (!mmc->ocr_avail) in dw_mci_init_slot()
2941 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; in dw_mci_init_slot()
2952 if (host->use_dma == TRANS_MODE_IDMAC) { in dw_mci_init_slot()
2953 mmc->max_segs = host->ring_size; in dw_mci_init_slot()
2954 mmc->max_blk_size = 65535; in dw_mci_init_slot()
2955 mmc->max_seg_size = 0x1000; in dw_mci_init_slot()
2956 mmc->max_req_size = mmc->max_seg_size * host->ring_size; in dw_mci_init_slot()
2957 mmc->max_blk_count = mmc->max_req_size / 512; in dw_mci_init_slot()
2958 } else if (host->use_dma == TRANS_MODE_EDMAC) { in dw_mci_init_slot()
2959 mmc->max_segs = 64; in dw_mci_init_slot()
2960 mmc->max_blk_size = 65535; in dw_mci_init_slot()
2961 mmc->max_blk_count = 65535; in dw_mci_init_slot()
2962 mmc->max_req_size = in dw_mci_init_slot()
2963 mmc->max_blk_size * mmc->max_blk_count; in dw_mci_init_slot()
2964 mmc->max_seg_size = mmc->max_req_size; in dw_mci_init_slot()
2967 mmc->max_segs = 64; in dw_mci_init_slot()
2968 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ in dw_mci_init_slot()
2969 mmc->max_blk_count = 512; in dw_mci_init_slot()
2970 mmc->max_req_size = mmc->max_blk_size * in dw_mci_init_slot()
2971 mmc->max_blk_count; in dw_mci_init_slot()
2972 mmc->max_seg_size = mmc->max_req_size; in dw_mci_init_slot()
2995 mmc_remove_host(slot->mmc); in dw_mci_cleanup_slot()
2996 slot->host->slot = NULL; in dw_mci_cleanup_slot()
2997 mmc_free_host(slot->mmc); in dw_mci_cleanup_slot()
3003 struct device *dev = host->dev; in dw_mci_init_dma()
3008 * 2b'00: No DMA Interface -> Actually means using Internal DMA block in dw_mci_init_dma()
3009 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block in dw_mci_init_dma()
3010 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block in dw_mci_init_dma()
3011 * 2b'11: Non DW DMA Interface -> pio only in dw_mci_init_dma()
3016 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); in dw_mci_init_dma()
3017 if (host->use_dma == DMA_INTERFACE_IDMA) { in dw_mci_init_dma()
3018 host->use_dma = TRANS_MODE_IDMAC; in dw_mci_init_dma()
3019 } else if (host->use_dma == DMA_INTERFACE_DWDMA || in dw_mci_init_dma()
3020 host->use_dma == DMA_INTERFACE_GDMA) { in dw_mci_init_dma()
3021 host->use_dma = TRANS_MODE_EDMAC; in dw_mci_init_dma()
3027 if (host->use_dma == TRANS_MODE_IDMAC) { in dw_mci_init_dma()
3035 /* host supports IDMAC in 64-bit address mode */ in dw_mci_init_dma()
3036 host->dma_64bit_address = 1; in dw_mci_init_dma()
3037 dev_info(host->dev, in dw_mci_init_dma()
3038 "IDMAC supports 64-bit address mode.\n"); in dw_mci_init_dma()
3039 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) in dw_mci_init_dma()
3040 dma_set_coherent_mask(host->dev, in dw_mci_init_dma()
3043 /* host supports IDMAC in 32-bit address mode */ in dw_mci_init_dma()
3044 host->dma_64bit_address = 0; in dw_mci_init_dma()
3045 dev_info(host->dev, in dw_mci_init_dma()
3046 "IDMAC supports 32-bit address mode.\n"); in dw_mci_init_dma()
3050 host->sg_cpu = dmam_alloc_coherent(host->dev, in dw_mci_init_dma()
3052 &host->sg_dma, GFP_KERNEL); in dw_mci_init_dma()
3053 if (!host->sg_cpu) { in dw_mci_init_dma()
3054 dev_err(host->dev, in dw_mci_init_dma()
3060 host->dma_ops = &dw_mci_idmac_ops; in dw_mci_init_dma()
3061 dev_info(host->dev, "Using internal DMA controller.\n"); in dw_mci_init_dma()
3064 if ((device_property_string_array_count(dev, "dma-names") < 0) || in dw_mci_init_dma()
3068 host->dma_ops = &dw_mci_edmac_ops; in dw_mci_init_dma()
3069 dev_info(host->dev, "Using external DMA controller.\n"); in dw_mci_init_dma()
3072 if (host->dma_ops->init && host->dma_ops->start && in dw_mci_init_dma()
3073 host->dma_ops->stop && host->dma_ops->cleanup) { in dw_mci_init_dma()
3074 if (host->dma_ops->init(host)) { in dw_mci_init_dma()
3075 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", in dw_mci_init_dma()
3080 dev_err(host->dev, "DMA initialization not found.\n"); in dw_mci_init_dma()
3087 dev_info(host->dev, "Using PIO mode.\n"); in dw_mci_init_dma()
3088 host->use_dma = TRANS_MODE_PIO; in dw_mci_init_dma()
3095 if (host->state != STATE_SENDING_CMD11) { in dw_mci_cmd11_timer()
3096 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); in dw_mci_cmd11_timer()
3100 host->cmd_status = SDMMC_INT_RTO; in dw_mci_cmd11_timer()
3101 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cmd11_timer()
3102 tasklet_schedule(&host->tasklet); in dw_mci_cmd11_timer()
3111 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_cto_timer()
3119 * pending command in the controller--we just assume it will never come. in dw_mci_cto_timer()
3121 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_cto_timer()
3124 dev_warn(host->dev, "Unexpected interrupt latency\n"); in dw_mci_cto_timer()
3127 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { in dw_mci_cto_timer()
3129 dev_warn(host->dev, "CTO timeout when already completed\n"); in dw_mci_cto_timer()
3137 switch (host->state) { in dw_mci_cto_timer()
3146 host->cmd_status = SDMMC_INT_RTO; in dw_mci_cto_timer()
3147 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cto_timer()
3148 tasklet_schedule(&host->tasklet); in dw_mci_cto_timer()
3151 dev_warn(host->dev, "Unexpected command timeout, state %d\n", in dw_mci_cto_timer()
3152 host->state); in dw_mci_cto_timer()
3157 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_cto_timer()
3166 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_dto_timer()
3172 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_dto_timer()
3175 dev_warn(host->dev, "Unexpected data interrupt latency\n"); in dw_mci_dto_timer()
3178 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { in dw_mci_dto_timer()
3180 dev_warn(host->dev, "DTO timeout when already completed\n"); in dw_mci_dto_timer()
3188 switch (host->state) { in dw_mci_dto_timer()
3196 host->data_status = SDMMC_INT_DRTO; in dw_mci_dto_timer()
3197 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_dto_timer()
3198 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_dto_timer()
3199 tasklet_schedule(&host->tasklet); in dw_mci_dto_timer()
3202 dev_warn(host->dev, "Unexpected data timeout, state %d\n", in dw_mci_dto_timer()
3203 host->state); in dw_mci_dto_timer()
3208 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_dto_timer()
3215 struct device *dev = host->dev; in dw_mci_parse_dt()
3216 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_parse_dt()
3222 return ERR_PTR(-ENOMEM); in dw_mci_parse_dt()
3225 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); in dw_mci_parse_dt()
3226 if (IS_ERR(pdata->rstc)) in dw_mci_parse_dt()
3227 return ERR_CAST(pdata->rstc); in dw_mci_parse_dt()
3229 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) in dw_mci_parse_dt()
3231 "fifo-depth property not found, using value of FIFOTH register as default\n"); in dw_mci_parse_dt()
3233 device_property_read_u32(dev, "card-detect-delay", in dw_mci_parse_dt()
3234 &pdata->detect_delay_ms); in dw_mci_parse_dt()
3236 device_property_read_u32(dev, "data-addr", &host->data_addr_override); in dw_mci_parse_dt()
3238 if (device_property_present(dev, "fifo-watermark-aligned")) in dw_mci_parse_dt()
3239 host->wm_aligned = true; in dw_mci_parse_dt()
3241 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) in dw_mci_parse_dt()
3242 pdata->bus_hz = clock_frequency; in dw_mci_parse_dt()
3244 if (drv_data && drv_data->parse_dt) { in dw_mci_parse_dt()
3245 ret = drv_data->parse_dt(host); in dw_mci_parse_dt()
3256 return ERR_PTR(-EINVAL); in dw_mci_parse_dt()
3266 * No need for CD if all slots have a non-error GPIO in dw_mci_enable_cd()
3269 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) in dw_mci_enable_cd()
3272 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { in dw_mci_enable_cd()
3273 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_enable_cd()
3277 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_enable_cd()
3283 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_probe()
3287 if (!host->pdata) { in dw_mci_probe()
3288 host->pdata = dw_mci_parse_dt(host); in dw_mci_probe()
3289 if (IS_ERR(host->pdata)) in dw_mci_probe()
3290 return dev_err_probe(host->dev, PTR_ERR(host->pdata), in dw_mci_probe()
3294 host->biu_clk = devm_clk_get(host->dev, "biu"); in dw_mci_probe()
3295 if (IS_ERR(host->biu_clk)) { in dw_mci_probe()
3296 dev_dbg(host->dev, "biu clock not available\n"); in dw_mci_probe()
3297 ret = PTR_ERR(host->biu_clk); in dw_mci_probe()
3298 if (ret == -EPROBE_DEFER) in dw_mci_probe()
3302 ret = clk_prepare_enable(host->biu_clk); in dw_mci_probe()
3304 dev_err(host->dev, "failed to enable biu clock\n"); in dw_mci_probe()
3309 host->ciu_clk = devm_clk_get(host->dev, "ciu"); in dw_mci_probe()
3310 if (IS_ERR(host->ciu_clk)) { in dw_mci_probe()
3311 dev_dbg(host->dev, "ciu clock not available\n"); in dw_mci_probe()
3312 ret = PTR_ERR(host->ciu_clk); in dw_mci_probe()
3313 if (ret == -EPROBE_DEFER) in dw_mci_probe()
3316 host->bus_hz = host->pdata->bus_hz; in dw_mci_probe()
3318 ret = clk_prepare_enable(host->ciu_clk); in dw_mci_probe()
3320 dev_err(host->dev, "failed to enable ciu clock\n"); in dw_mci_probe()
3324 if (host->pdata->bus_hz) { in dw_mci_probe()
3325 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); in dw_mci_probe()
3327 dev_warn(host->dev, in dw_mci_probe()
3329 host->pdata->bus_hz); in dw_mci_probe()
3331 host->bus_hz = clk_get_rate(host->ciu_clk); in dw_mci_probe()
3334 if (!host->bus_hz) { in dw_mci_probe()
3335 dev_err(host->dev, in dw_mci_probe()
3337 ret = -ENODEV; in dw_mci_probe()
3341 if (host->pdata->rstc) { in dw_mci_probe()
3342 reset_control_assert(host->pdata->rstc); in dw_mci_probe()
3344 reset_control_deassert(host->pdata->rstc); in dw_mci_probe()
3347 if (drv_data && drv_data->init) { in dw_mci_probe()
3348 ret = drv_data->init(host); in dw_mci_probe()
3350 dev_err(host->dev, in dw_mci_probe()
3356 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); in dw_mci_probe()
3357 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); in dw_mci_probe()
3358 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); in dw_mci_probe()
3360 spin_lock_init(&host->lock); in dw_mci_probe()
3361 spin_lock_init(&host->irq_lock); in dw_mci_probe()
3362 INIT_LIST_HEAD(&host->queue); in dw_mci_probe()
3367 * Get the host data width - this assumes that HCON has been set with in dw_mci_probe()
3372 host->push_data = dw_mci_push_data16; in dw_mci_probe()
3373 host->pull_data = dw_mci_pull_data16; in dw_mci_probe()
3375 host->data_shift = 1; in dw_mci_probe()
3377 host->push_data = dw_mci_push_data64; in dw_mci_probe()
3378 host->pull_data = dw_mci_pull_data64; in dw_mci_probe()
3380 host->data_shift = 3; in dw_mci_probe()
3385 "Defaulting to 32-bit access.\n"); in dw_mci_probe()
3386 host->push_data = dw_mci_push_data32; in dw_mci_probe()
3387 host->pull_data = dw_mci_pull_data32; in dw_mci_probe()
3389 host->data_shift = 2; in dw_mci_probe()
3394 ret = -ENODEV; in dw_mci_probe()
3398 host->dma_ops = host->pdata->dma_ops; in dw_mci_probe()
3409 * FIFO threshold settings RxMark = fifo_size / 2 - 1, in dw_mci_probe()
3412 if (!host->pdata->fifo_depth) { in dw_mci_probe()
3414 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may in dw_mci_probe()
3422 fifo_size = host->pdata->fifo_depth; in dw_mci_probe()
3424 host->fifo_depth = fifo_size; in dw_mci_probe()
3425 host->fifoth_val = in dw_mci_probe()
3426 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); in dw_mci_probe()
3427 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_probe()
3435 * Need to check the version-id and set data-offset for DATA register. in dw_mci_probe()
3437 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); in dw_mci_probe()
3438 dev_info(host->dev, "Version ID is %04x\n", host->verid); in dw_mci_probe()
3440 if (host->data_addr_override) in dw_mci_probe()
3441 host->fifo_reg = host->regs + host->data_addr_override; in dw_mci_probe()
3442 else if (host->verid < DW_MMC_240A) in dw_mci_probe()
3443 host->fifo_reg = host->regs + DATA_OFFSET; in dw_mci_probe()
3445 host->fifo_reg = host->regs + DATA_240A_OFFSET; in dw_mci_probe()
3447 tasklet_setup(&host->tasklet, dw_mci_tasklet_func); in dw_mci_probe()
3448 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, in dw_mci_probe()
3449 host->irq_flags, "dw-mci", host); in dw_mci_probe()
3463 dev_info(host->dev, in dw_mci_probe()
3464 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", in dw_mci_probe()
3465 host->irq, width, fifo_size); in dw_mci_probe()
3470 dev_dbg(host->dev, "slot %d init failed\n", i); in dw_mci_probe()
3480 if (host->use_dma && host->dma_ops->exit) in dw_mci_probe()
3481 host->dma_ops->exit(host); in dw_mci_probe()
3483 reset_control_assert(host->pdata->rstc); in dw_mci_probe()
3486 clk_disable_unprepare(host->ciu_clk); in dw_mci_probe()
3489 clk_disable_unprepare(host->biu_clk); in dw_mci_probe()
3497 dev_dbg(host->dev, "remove slot\n"); in dw_mci_remove()
3498 if (host->slot) in dw_mci_remove()
3499 dw_mci_cleanup_slot(host->slot); in dw_mci_remove()
3508 if (host->use_dma && host->dma_ops->exit) in dw_mci_remove()
3509 host->dma_ops->exit(host); in dw_mci_remove()
3511 reset_control_assert(host->pdata->rstc); in dw_mci_remove()
3513 clk_disable_unprepare(host->ciu_clk); in dw_mci_remove()
3514 clk_disable_unprepare(host->biu_clk); in dw_mci_remove()
3525 if (host->use_dma && host->dma_ops->exit) in dw_mci_runtime_suspend()
3526 host->dma_ops->exit(host); in dw_mci_runtime_suspend()
3528 clk_disable_unprepare(host->ciu_clk); in dw_mci_runtime_suspend()
3530 if (host->slot && in dw_mci_runtime_suspend()
3531 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_suspend()
3532 !mmc_card_is_removable(host->slot->mmc))) in dw_mci_runtime_suspend()
3533 clk_disable_unprepare(host->biu_clk); in dw_mci_runtime_suspend()
3544 if (host->slot && in dw_mci_runtime_resume()
3545 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_resume()
3546 !mmc_card_is_removable(host->slot->mmc))) { in dw_mci_runtime_resume()
3547 ret = clk_prepare_enable(host->biu_clk); in dw_mci_runtime_resume()
3552 ret = clk_prepare_enable(host->ciu_clk); in dw_mci_runtime_resume()
3557 clk_disable_unprepare(host->ciu_clk); in dw_mci_runtime_resume()
3558 ret = -ENODEV; in dw_mci_runtime_resume()
3562 if (host->use_dma && host->dma_ops->init) in dw_mci_runtime_resume()
3563 host->dma_ops->init(host); in dw_mci_runtime_resume()
3569 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_runtime_resume()
3570 host->prev_blksz = 0; in dw_mci_runtime_resume()
3582 if (host->slot && host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) in dw_mci_runtime_resume()
3583 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); in dw_mci_runtime_resume()
3586 dw_mci_setup_bus(host->slot, true); in dw_mci_runtime_resume()
3588 /* Re-enable SDIO interrupts. */ in dw_mci_runtime_resume()
3589 if (sdio_irq_claimed(host->slot->mmc)) in dw_mci_runtime_resume()
3590 __dw_mci_enable_sdio_irq(host->slot, 1); in dw_mci_runtime_resume()
3598 if (host->slot && in dw_mci_runtime_resume()
3599 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_resume()
3600 !mmc_card_is_removable(host->slot->mmc))) in dw_mci_runtime_resume()
3601 clk_disable_unprepare(host->biu_clk); in dw_mci_runtime_resume()
3610 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); in dw_mci_init()
3621 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");