Lines Matching +full:no +full:- +full:mmc
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
16 #include <linux/mmc/host.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/mmc/mmc.h>
24 #include <linux/mmc/slot-gpio.h>
27 #include <linux/platform_data/mmc-davinci.h>
37 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */
38 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */
144 #define MAX_CCNT ((1 << 16) - 1)
170 struct mmc_host *mmc; member
202 /* Version of the MMC/SD controller */
218 host->buffer_bytes_left = sg_dma_len(host->sg); in mmc_davinci_sg_to_buf()
219 host->buffer = sg_virt(host->sg); in mmc_davinci_sg_to_buf()
220 if (host->buffer_bytes_left > host->bytes_left) in mmc_davinci_sg_to_buf()
221 host->buffer_bytes_left = host->bytes_left; in mmc_davinci_sg_to_buf()
230 if (host->buffer_bytes_left == 0) { in davinci_fifo_data_trans()
231 host->sg = sg_next(host->data->sg); in davinci_fifo_data_trans()
235 p = host->buffer; in davinci_fifo_data_trans()
236 if (n > host->buffer_bytes_left) in davinci_fifo_data_trans()
237 n = host->buffer_bytes_left; in davinci_fifo_data_trans()
238 host->buffer_bytes_left -= n; in davinci_fifo_data_trans()
239 host->bytes_left -= n; in davinci_fifo_data_trans()
242 * to/from the fifo here; there's no I/O overlap. in davinci_fifo_data_trans()
245 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { in davinci_fifo_data_trans()
247 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); in davinci_fifo_data_trans()
251 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); in davinci_fifo_data_trans()
256 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); in davinci_fifo_data_trans()
260 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); in davinci_fifo_data_trans()
264 host->buffer = p; in davinci_fifo_data_trans()
273 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", in mmc_davinci_start_command()
274 cmd->opcode, cmd->arg, in mmc_davinci_start_command()
293 host->cmd = cmd; in mmc_davinci_start_command()
309 case MMC_RSP_R3: /* 48 bits, no CRC */ in mmc_davinci_start_command()
314 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", in mmc_davinci_start_command()
320 cmd_reg |= cmd->opcode; in mmc_davinci_start_command()
323 if (host->do_dma) in mmc_davinci_start_command()
326 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && in mmc_davinci_start_command()
327 host->data_dir == DAVINCI_MMC_DATADIR_READ) in mmc_davinci_start_command()
331 if (cmd->data) in mmc_davinci_start_command()
335 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) in mmc_davinci_start_command()
338 if (host->bus_mode == MMC_BUSMODE_PUSHPULL) in mmc_davinci_start_command()
342 writel(0x1FFF, host->base + DAVINCI_MMCTOR); in mmc_davinci_start_command()
346 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { in mmc_davinci_start_command()
349 if (!host->do_dma) in mmc_davinci_start_command()
351 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { in mmc_davinci_start_command()
354 if (!host->do_dma) in mmc_davinci_start_command()
359 * Before non-DMA WRITE commands the controller needs priming: in mmc_davinci_start_command()
362 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) in mmc_davinci_start_command()
365 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); in mmc_davinci_start_command()
366 writel(cmd_reg, host->base + DAVINCI_MMCCMD); in mmc_davinci_start_command()
368 host->active_request = true; in mmc_davinci_start_command()
370 if (!host->do_dma && host->bytes_left <= poll_threshold) { in mmc_davinci_start_command()
373 while (host->active_request && count--) { in mmc_davinci_start_command()
379 if (host->active_request) in mmc_davinci_start_command()
380 writel(im_val, host->base + DAVINCI_MMCIM); in mmc_davinci_start_command()
383 /*----------------------------------------------------------------------*/
391 if (host->data_dir == DAVINCI_MMC_DATADIR_READ) in davinci_abort_dma()
392 sync_dev = host->dma_rx; in davinci_abort_dma()
394 sync_dev = host->dma_tx; in davinci_abort_dma()
406 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { in mmc_davinci_send_dma_request()
409 .dst_addr = host->mem_res->start + DAVINCI_MMCDXR, in mmc_davinci_send_dma_request()
414 chan = host->dma_tx; in mmc_davinci_send_dma_request()
415 dmaengine_slave_config(host->dma_tx, &dma_tx_conf); in mmc_davinci_send_dma_request()
417 desc = dmaengine_prep_slave_sg(host->dma_tx, in mmc_davinci_send_dma_request()
418 data->sg, in mmc_davinci_send_dma_request()
419 host->sg_len, in mmc_davinci_send_dma_request()
423 dev_dbg(mmc_dev(host->mmc), in mmc_davinci_send_dma_request()
425 ret = -1; in mmc_davinci_send_dma_request()
431 .src_addr = host->mem_res->start + DAVINCI_MMCDRR, in mmc_davinci_send_dma_request()
436 chan = host->dma_rx; in mmc_davinci_send_dma_request()
437 dmaengine_slave_config(host->dma_rx, &dma_rx_conf); in mmc_davinci_send_dma_request()
439 desc = dmaengine_prep_slave_sg(host->dma_rx, in mmc_davinci_send_dma_request()
440 data->sg, in mmc_davinci_send_dma_request()
441 host->sg_len, in mmc_davinci_send_dma_request()
445 dev_dbg(mmc_dev(host->mmc), in mmc_davinci_send_dma_request()
447 ret = -1; in mmc_davinci_send_dma_request()
463 int mask = rw_threshold - 1; in mmc_davinci_start_dma_transfer()
466 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, in mmc_davinci_start_dma_transfer()
469 /* no individual DMA segment should need a partial FIFO */ in mmc_davinci_start_dma_transfer()
470 for (i = 0; i < host->sg_len; i++) { in mmc_davinci_start_dma_transfer()
471 if (sg_dma_len(data->sg + i) & mask) { in mmc_davinci_start_dma_transfer()
472 dma_unmap_sg(mmc_dev(host->mmc), in mmc_davinci_start_dma_transfer()
473 data->sg, data->sg_len, in mmc_davinci_start_dma_transfer()
475 return -1; in mmc_davinci_start_dma_transfer()
479 host->do_dma = 1; in mmc_davinci_start_dma_transfer()
487 if (!host->use_dma) in davinci_release_dma_channels()
490 dma_release_channel(host->dma_tx); in davinci_release_dma_channels()
491 dma_release_channel(host->dma_rx); in davinci_release_dma_channels()
496 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); in davinci_acquire_dma_channels()
497 if (IS_ERR(host->dma_tx)) { in davinci_acquire_dma_channels()
498 dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); in davinci_acquire_dma_channels()
499 return PTR_ERR(host->dma_tx); in davinci_acquire_dma_channels()
502 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); in davinci_acquire_dma_channels()
503 if (IS_ERR(host->dma_rx)) { in davinci_acquire_dma_channels()
504 dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); in davinci_acquire_dma_channels()
505 dma_release_channel(host->dma_tx); in davinci_acquire_dma_channels()
506 return PTR_ERR(host->dma_rx); in davinci_acquire_dma_channels()
512 /*----------------------------------------------------------------------*/
519 struct mmc_data *data = req->data; in mmc_davinci_prepare_data()
521 if (host->version == MMC_CTLR_VERSION_2) in mmc_davinci_prepare_data()
524 host->data = data; in mmc_davinci_prepare_data()
526 host->data_dir = DAVINCI_MMC_DATADIR_NONE; in mmc_davinci_prepare_data()
527 writel(0, host->base + DAVINCI_MMCBLEN); in mmc_davinci_prepare_data()
528 writel(0, host->base + DAVINCI_MMCNBLK); in mmc_davinci_prepare_data()
532 dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n", in mmc_davinci_prepare_data()
533 (data->flags & MMC_DATA_WRITE) ? "write" : "read", in mmc_davinci_prepare_data()
534 data->blocks, data->blksz); in mmc_davinci_prepare_data()
535 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", in mmc_davinci_prepare_data()
536 data->timeout_clks, data->timeout_ns); in mmc_davinci_prepare_data()
537 timeout = data->timeout_clks + in mmc_davinci_prepare_data()
538 (data->timeout_ns / host->ns_in_one_cycle); in mmc_davinci_prepare_data()
542 writel(timeout, host->base + DAVINCI_MMCTOD); in mmc_davinci_prepare_data()
543 writel(data->blocks, host->base + DAVINCI_MMCNBLK); in mmc_davinci_prepare_data()
544 writel(data->blksz, host->base + DAVINCI_MMCBLEN); in mmc_davinci_prepare_data()
547 if (data->flags & MMC_DATA_WRITE) { in mmc_davinci_prepare_data()
548 host->data_dir = DAVINCI_MMC_DATADIR_WRITE; in mmc_davinci_prepare_data()
550 host->base + DAVINCI_MMCFIFOCTL); in mmc_davinci_prepare_data()
552 host->base + DAVINCI_MMCFIFOCTL); in mmc_davinci_prepare_data()
554 host->data_dir = DAVINCI_MMC_DATADIR_READ; in mmc_davinci_prepare_data()
556 host->base + DAVINCI_MMCFIFOCTL); in mmc_davinci_prepare_data()
558 host->base + DAVINCI_MMCFIFOCTL); in mmc_davinci_prepare_data()
561 host->buffer = NULL; in mmc_davinci_prepare_data()
562 host->bytes_left = data->blocks * data->blksz; in mmc_davinci_prepare_data()
572 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 in mmc_davinci_prepare_data()
574 /* zero this to ensure we take no PIO paths */ in mmc_davinci_prepare_data()
575 host->bytes_left = 0; in mmc_davinci_prepare_data()
578 host->sg_len = data->sg_len; in mmc_davinci_prepare_data()
579 host->sg = host->data->sg; in mmc_davinci_prepare_data()
584 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) in mmc_davinci_request() argument
586 struct mmc_davinci_host *host = mmc_priv(mmc); in mmc_davinci_request()
594 mmcst1 = readl(host->base + DAVINCI_MMCST1); in mmc_davinci_request()
600 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); in mmc_davinci_request()
601 req->cmd->error = -ETIMEDOUT; in mmc_davinci_request()
602 mmc_request_done(mmc, req); in mmc_davinci_request()
606 host->do_dma = 0; in mmc_davinci_request()
608 mmc_davinci_start_command(host, req->cmd); in mmc_davinci_request()
616 mmc_pclk = host->mmc_input_clk; in calculate_freq_for_card()
619 / (2 * mmc_req_freq)) - 1; in calculate_freq_for_card()
630 host->ns_in_one_cycle = (1000000) / (((mmc_pclk in calculate_freq_for_card()
633 host->ns_in_one_cycle = (1000000) / (((mmc_pclk in calculate_freq_for_card()
639 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) in calculate_clk_divider() argument
643 struct mmc_davinci_host *host = mmc_priv(mmc); in calculate_clk_divider()
645 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { in calculate_clk_divider()
652 / (2 * MMCSD_INIT_CLOCK)) - 1; in calculate_clk_divider()
657 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; in calculate_clk_divider()
659 writel(temp, host->base + DAVINCI_MMCCLK); in calculate_clk_divider()
662 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); in calculate_clk_divider()
665 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); in calculate_clk_divider()
670 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; in calculate_clk_divider()
671 writel(temp, host->base + DAVINCI_MMCCLK); in calculate_clk_divider()
675 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; in calculate_clk_divider()
677 writel(temp, host->base + DAVINCI_MMCCLK); in calculate_clk_divider()
679 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); in calculate_clk_divider()
685 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) in mmc_davinci_set_ios() argument
687 struct mmc_davinci_host *host = mmc_priv(mmc); in mmc_davinci_set_ios()
688 struct platform_device *pdev = to_platform_device(mmc->parent); in mmc_davinci_set_ios()
689 struct davinci_mmc_config *config = pdev->dev.platform_data; in mmc_davinci_set_ios()
691 dev_dbg(mmc_dev(host->mmc), in mmc_davinci_set_ios()
693 ios->clock, ios->bus_mode, ios->power_mode, in mmc_davinci_set_ios()
694 ios->vdd); in mmc_davinci_set_ios()
696 switch (ios->power_mode) { in mmc_davinci_set_ios()
698 if (config && config->set_power) in mmc_davinci_set_ios()
699 config->set_power(pdev->id, false); in mmc_davinci_set_ios()
702 if (config && config->set_power) in mmc_davinci_set_ios()
703 config->set_power(pdev->id, true); in mmc_davinci_set_ios()
707 switch (ios->bus_width) { in mmc_davinci_set_ios()
709 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); in mmc_davinci_set_ios()
710 writel((readl(host->base + DAVINCI_MMCCTL) & in mmc_davinci_set_ios()
712 host->base + DAVINCI_MMCCTL); in mmc_davinci_set_ios()
715 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); in mmc_davinci_set_ios()
716 if (host->version == MMC_CTLR_VERSION_2) in mmc_davinci_set_ios()
717 writel((readl(host->base + DAVINCI_MMCCTL) & in mmc_davinci_set_ios()
719 host->base + DAVINCI_MMCCTL); in mmc_davinci_set_ios()
721 writel(readl(host->base + DAVINCI_MMCCTL) | in mmc_davinci_set_ios()
723 host->base + DAVINCI_MMCCTL); in mmc_davinci_set_ios()
726 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); in mmc_davinci_set_ios()
727 if (host->version == MMC_CTLR_VERSION_2) in mmc_davinci_set_ios()
728 writel(readl(host->base + DAVINCI_MMCCTL) & in mmc_davinci_set_ios()
730 host->base + DAVINCI_MMCCTL); in mmc_davinci_set_ios()
732 writel(readl(host->base + DAVINCI_MMCCTL) & in mmc_davinci_set_ios()
734 host->base + DAVINCI_MMCCTL); in mmc_davinci_set_ios()
738 calculate_clk_divider(mmc, ios); in mmc_davinci_set_ios()
740 host->bus_mode = ios->bus_mode; in mmc_davinci_set_ios()
741 if (ios->power_mode == MMC_POWER_UP) { in mmc_davinci_set_ios()
746 writel(0, host->base + DAVINCI_MMCARGHL); in mmc_davinci_set_ios()
747 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); in mmc_davinci_set_ios()
749 u32 tmp = readl(host->base + DAVINCI_MMCST0); in mmc_davinci_set_ios()
758 dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); in mmc_davinci_set_ios()
767 host->data = NULL; in mmc_davinci_xfer_done()
769 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { in mmc_davinci_xfer_done()
771 * SDIO Interrupt Detection work-around as suggested by in mmc_davinci_xfer_done()
775 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & in mmc_davinci_xfer_done()
777 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); in mmc_davinci_xfer_done()
778 mmc_signal_sdio_irq(host->mmc); in mmc_davinci_xfer_done()
782 if (host->do_dma) { in mmc_davinci_xfer_done()
785 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, in mmc_davinci_xfer_done()
787 host->do_dma = false; in mmc_davinci_xfer_done()
789 host->data_dir = DAVINCI_MMC_DATADIR_NONE; in mmc_davinci_xfer_done()
791 if (!data->stop || (host->cmd && host->cmd->error)) { in mmc_davinci_xfer_done()
792 mmc_request_done(host->mmc, data->mrq); in mmc_davinci_xfer_done()
793 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_xfer_done()
794 host->active_request = false; in mmc_davinci_xfer_done()
796 mmc_davinci_start_command(host, data->stop); in mmc_davinci_xfer_done()
802 host->cmd = NULL; in mmc_davinci_cmd_done()
804 if (cmd->flags & MMC_RSP_PRESENT) { in mmc_davinci_cmd_done()
805 if (cmd->flags & MMC_RSP_136) { in mmc_davinci_cmd_done()
807 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); in mmc_davinci_cmd_done()
808 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); in mmc_davinci_cmd_done()
809 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); in mmc_davinci_cmd_done()
810 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); in mmc_davinci_cmd_done()
813 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); in mmc_davinci_cmd_done()
817 if (host->data == NULL || cmd->error) { in mmc_davinci_cmd_done()
818 if (cmd->error == -ETIMEDOUT) in mmc_davinci_cmd_done()
819 cmd->mrq->cmd->retries = 0; in mmc_davinci_cmd_done()
820 mmc_request_done(host->mmc, cmd->mrq); in mmc_davinci_cmd_done()
821 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_cmd_done()
822 host->active_request = false; in mmc_davinci_cmd_done()
831 temp = readl(host->base + DAVINCI_MMCCTL); in mmc_davinci_reset_ctrl()
837 writel(temp, host->base + DAVINCI_MMCCTL); in mmc_davinci_reset_ctrl()
853 status = readl(host->base + DAVINCI_SDIOIST); in mmc_davinci_sdio_irq()
855 dev_dbg(mmc_dev(host->mmc), in mmc_davinci_sdio_irq()
857 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); in mmc_davinci_sdio_irq()
858 mmc_signal_sdio_irq(host->mmc); in mmc_davinci_sdio_irq()
869 struct mmc_data *data = host->data; in mmc_davinci_irq()
871 if (host->cmd == NULL && host->data == NULL) { in mmc_davinci_irq()
872 status = readl(host->base + DAVINCI_MMCST0); in mmc_davinci_irq()
873 dev_dbg(mmc_dev(host->mmc), in mmc_davinci_irq()
876 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
880 status = readl(host->base + DAVINCI_MMCST0); in mmc_davinci_irq()
888 * non-dma. in mmc_davinci_irq()
890 if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { in mmc_davinci_irq()
900 im_val = readl(host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
901 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
905 status = readl(host->base + DAVINCI_MMCST0); in mmc_davinci_irq()
907 } while (host->bytes_left && in mmc_davinci_irq()
914 * status is race-prone. in mmc_davinci_irq()
916 writel(im_val, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
922 if ((host->do_dma == 0) && (host->bytes_left > 0)) { in mmc_davinci_irq()
924 * no RX ints are generated in mmc_davinci_irq()
926 davinci_fifo_data_trans(host, host->bytes_left); in mmc_davinci_irq()
929 data->bytes_xfered = data->blocks * data->blksz; in mmc_davinci_irq()
931 dev_err(mmc_dev(host->mmc), in mmc_davinci_irq()
932 "DATDNE with no host->data\n"); in mmc_davinci_irq()
938 data->error = -ETIMEDOUT; in mmc_davinci_irq()
941 dev_dbg(mmc_dev(host->mmc), in mmc_davinci_irq()
950 data->error = -EILSEQ; in mmc_davinci_irq()
956 * case and the two three-bit patterns in various SD specs in mmc_davinci_irq()
960 u32 temp = readb(host->base + DAVINCI_MMCDRSP); in mmc_davinci_irq()
963 data->error = -ETIMEDOUT; in mmc_davinci_irq()
965 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", in mmc_davinci_irq()
967 (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); in mmc_davinci_irq()
974 if (host->cmd) { in mmc_davinci_irq()
975 dev_dbg(mmc_dev(host->mmc), in mmc_davinci_irq()
977 host->cmd->opcode, qstatus); in mmc_davinci_irq()
978 host->cmd->error = -ETIMEDOUT; in mmc_davinci_irq()
989 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); in mmc_davinci_irq()
990 if (host->cmd) { in mmc_davinci_irq()
991 host->cmd->error = -EILSEQ; in mmc_davinci_irq()
998 end_command = host->cmd ? 1 : 0; in mmc_davinci_irq()
1002 mmc_davinci_cmd_done(host, host->cmd); in mmc_davinci_irq()
1008 static int mmc_davinci_get_cd(struct mmc_host *mmc) in mmc_davinci_get_cd() argument
1010 struct platform_device *pdev = to_platform_device(mmc->parent); in mmc_davinci_get_cd()
1011 struct davinci_mmc_config *config = pdev->dev.platform_data; in mmc_davinci_get_cd()
1013 if (config && config->get_cd) in mmc_davinci_get_cd()
1014 return config->get_cd(pdev->id); in mmc_davinci_get_cd()
1016 return mmc_gpio_get_cd(mmc); in mmc_davinci_get_cd()
1019 static int mmc_davinci_get_ro(struct mmc_host *mmc) in mmc_davinci_get_ro() argument
1021 struct platform_device *pdev = to_platform_device(mmc->parent); in mmc_davinci_get_ro()
1022 struct davinci_mmc_config *config = pdev->dev.platform_data; in mmc_davinci_get_ro()
1024 if (config && config->get_ro) in mmc_davinci_get_ro()
1025 return config->get_ro(pdev->id); in mmc_davinci_get_ro()
1027 return mmc_gpio_get_ro(mmc); in mmc_davinci_get_ro()
1030 static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) in mmc_davinci_enable_sdio_irq() argument
1032 struct mmc_davinci_host *host = mmc_priv(mmc); in mmc_davinci_enable_sdio_irq()
1035 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { in mmc_davinci_enable_sdio_irq()
1036 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); in mmc_davinci_enable_sdio_irq()
1037 mmc_signal_sdio_irq(host->mmc); in mmc_davinci_enable_sdio_irq()
1039 host->sdio_int = true; in mmc_davinci_enable_sdio_irq()
1040 writel(readl(host->base + DAVINCI_SDIOIEN) | in mmc_davinci_enable_sdio_irq()
1041 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); in mmc_davinci_enable_sdio_irq()
1044 host->sdio_int = false; in mmc_davinci_enable_sdio_irq()
1045 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, in mmc_davinci_enable_sdio_irq()
1046 host->base + DAVINCI_SDIOIEN); in mmc_davinci_enable_sdio_irq()
1058 /*----------------------------------------------------------------------*/
1066 struct mmc_host *mmc; in mmc_davinci_cpufreq_transition() local
1070 mmc = host->mmc; in mmc_davinci_cpufreq_transition()
1071 mmc_pclk = clk_get_rate(host->clk); in mmc_davinci_cpufreq_transition()
1074 spin_lock_irqsave(&mmc->lock, flags); in mmc_davinci_cpufreq_transition()
1075 host->mmc_input_clk = mmc_pclk; in mmc_davinci_cpufreq_transition()
1076 calculate_clk_divider(mmc, &mmc->ios); in mmc_davinci_cpufreq_transition()
1077 spin_unlock_irqrestore(&mmc->lock, flags); in mmc_davinci_cpufreq_transition()
1085 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; in mmc_davinci_cpufreq_register()
1087 return cpufreq_register_notifier(&host->freq_transition, in mmc_davinci_cpufreq_register()
1093 cpufreq_unregister_notifier(&host->freq_transition, in mmc_davinci_cpufreq_deregister()
1111 writel(0, host->base + DAVINCI_MMCCLK); in init_mmcsd_host()
1112 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); in init_mmcsd_host()
1114 writel(0x1FFF, host->base + DAVINCI_MMCTOR); in init_mmcsd_host()
1115 writel(0xFFFF, host->base + DAVINCI_MMCTOD); in init_mmcsd_host()
1122 .name = "dm6441-mmc",
1125 .name = "da830-mmc",
1134 .compatible = "ti,dm6441-mmc",
1138 .compatible = "ti,da830-mmc",
1145 static int mmc_davinci_parse_pdata(struct mmc_host *mmc) in mmc_davinci_parse_pdata() argument
1147 struct platform_device *pdev = to_platform_device(mmc->parent); in mmc_davinci_parse_pdata()
1148 struct davinci_mmc_config *pdata = pdev->dev.platform_data; in mmc_davinci_parse_pdata()
1153 return -EINVAL; in mmc_davinci_parse_pdata()
1155 host = mmc_priv(mmc); in mmc_davinci_parse_pdata()
1157 return -EINVAL; in mmc_davinci_parse_pdata()
1159 if (pdata && pdata->nr_sg) in mmc_davinci_parse_pdata()
1160 host->nr_sg = pdata->nr_sg - 1; in mmc_davinci_parse_pdata()
1162 if (pdata && (pdata->wires == 4 || pdata->wires == 0)) in mmc_davinci_parse_pdata()
1163 mmc->caps |= MMC_CAP_4_BIT_DATA; in mmc_davinci_parse_pdata()
1165 if (pdata && (pdata->wires == 8)) in mmc_davinci_parse_pdata()
1166 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); in mmc_davinci_parse_pdata()
1168 mmc->f_min = 312500; in mmc_davinci_parse_pdata()
1169 mmc->f_max = 25000000; in mmc_davinci_parse_pdata()
1170 if (pdata && pdata->max_freq) in mmc_davinci_parse_pdata()
1171 mmc->f_max = pdata->max_freq; in mmc_davinci_parse_pdata()
1172 if (pdata && pdata->caps) in mmc_davinci_parse_pdata()
1173 mmc->caps |= pdata->caps; in mmc_davinci_parse_pdata()
1176 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); in mmc_davinci_parse_pdata()
1177 if (ret == -EPROBE_DEFER) in mmc_davinci_parse_pdata()
1180 mmc->caps |= MMC_CAP_NEEDS_POLL; in mmc_davinci_parse_pdata()
1182 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); in mmc_davinci_parse_pdata()
1183 if (ret == -EPROBE_DEFER) in mmc_davinci_parse_pdata()
1192 struct mmc_host *mmc = NULL; in davinci_mmcsd_probe() local
1200 return -ENODEV; in davinci_mmcsd_probe()
1206 mem = devm_request_mem_region(&pdev->dev, r->start, mem_size, in davinci_mmcsd_probe()
1207 pdev->name); in davinci_mmcsd_probe()
1209 return -EBUSY; in davinci_mmcsd_probe()
1211 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); in davinci_mmcsd_probe()
1212 if (!mmc) in davinci_mmcsd_probe()
1213 return -ENOMEM; in davinci_mmcsd_probe()
1215 host = mmc_priv(mmc); in davinci_mmcsd_probe()
1216 host->mmc = mmc; /* Important */ in davinci_mmcsd_probe()
1218 host->mem_res = mem; in davinci_mmcsd_probe()
1219 host->base = devm_ioremap(&pdev->dev, mem->start, mem_size); in davinci_mmcsd_probe()
1220 if (!host->base) { in davinci_mmcsd_probe()
1221 ret = -ENOMEM; in davinci_mmcsd_probe()
1225 host->clk = devm_clk_get(&pdev->dev, NULL); in davinci_mmcsd_probe()
1226 if (IS_ERR(host->clk)) { in davinci_mmcsd_probe()
1227 ret = PTR_ERR(host->clk); in davinci_mmcsd_probe()
1230 ret = clk_prepare_enable(host->clk); in davinci_mmcsd_probe()
1234 host->mmc_input_clk = clk_get_rate(host->clk); in davinci_mmcsd_probe()
1236 pdev->id_entry = of_device_get_match_data(&pdev->dev); in davinci_mmcsd_probe()
1237 if (pdev->id_entry) { in davinci_mmcsd_probe()
1238 ret = mmc_of_parse(mmc); in davinci_mmcsd_probe()
1240 dev_err_probe(&pdev->dev, ret, in davinci_mmcsd_probe()
1245 ret = mmc_davinci_parse_pdata(mmc); in davinci_mmcsd_probe()
1247 dev_err(&pdev->dev, in davinci_mmcsd_probe()
1252 if (host->nr_sg > MAX_NR_SG || !host->nr_sg) in davinci_mmcsd_probe()
1253 host->nr_sg = MAX_NR_SG; in davinci_mmcsd_probe()
1257 host->use_dma = use_dma; in davinci_mmcsd_probe()
1258 host->mmc_irq = irq; in davinci_mmcsd_probe()
1259 host->sdio_irq = platform_get_irq_optional(pdev, 1); in davinci_mmcsd_probe()
1261 if (host->use_dma) { in davinci_mmcsd_probe()
1263 if (ret == -EPROBE_DEFER) in davinci_mmcsd_probe()
1266 host->use_dma = 0; in davinci_mmcsd_probe()
1269 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in davinci_mmcsd_probe()
1273 host->version = id_entry->driver_data; in davinci_mmcsd_probe()
1275 mmc->ops = &mmc_davinci_ops; in davinci_mmcsd_probe()
1276 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; in davinci_mmcsd_probe()
1278 /* With no iommu coalescing pages, each phys_seg is a hw_seg. in davinci_mmcsd_probe()
1282 mmc->max_segs = MAX_NR_SG; in davinci_mmcsd_probe()
1285 mmc->max_seg_size = MAX_CCNT * rw_threshold; in davinci_mmcsd_probe()
1287 /* MMC/SD controller limits for multiblock requests */ in davinci_mmcsd_probe()
1288 mmc->max_blk_size = 4095; /* BLEN is 12 bits */ in davinci_mmcsd_probe()
1289 mmc->max_blk_count = 65535; /* NBLK is 16 bits */ in davinci_mmcsd_probe()
1290 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; in davinci_mmcsd_probe()
1292 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); in davinci_mmcsd_probe()
1293 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); in davinci_mmcsd_probe()
1294 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); in davinci_mmcsd_probe()
1295 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); in davinci_mmcsd_probe()
1301 dev_err(&pdev->dev, "failed to register cpufreq\n"); in davinci_mmcsd_probe()
1305 ret = mmc_add_host(mmc); in davinci_mmcsd_probe()
1309 ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0, in davinci_mmcsd_probe()
1310 mmc_hostname(mmc), host); in davinci_mmcsd_probe()
1314 if (host->sdio_irq >= 0) { in davinci_mmcsd_probe()
1315 ret = devm_request_irq(&pdev->dev, host->sdio_irq, in davinci_mmcsd_probe()
1317 mmc_hostname(mmc), host); in davinci_mmcsd_probe()
1319 mmc->caps |= MMC_CAP_SDIO_IRQ; in davinci_mmcsd_probe()
1322 rename_region(mem, mmc_hostname(mmc)); in davinci_mmcsd_probe()
1324 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", in davinci_mmcsd_probe()
1325 host->use_dma ? "DMA" : "PIO", in davinci_mmcsd_probe()
1326 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); in davinci_mmcsd_probe()
1331 mmc_remove_host(mmc); in davinci_mmcsd_probe()
1338 clk_disable_unprepare(host->clk); in davinci_mmcsd_probe()
1342 mmc_free_host(mmc); in davinci_mmcsd_probe()
1351 mmc_remove_host(host->mmc); in davinci_mmcsd_remove()
1354 clk_disable_unprepare(host->clk); in davinci_mmcsd_remove()
1355 mmc_free_host(host->mmc); in davinci_mmcsd_remove()
1363 writel(0, host->base + DAVINCI_MMCIM); in davinci_mmcsd_suspend()
1365 clk_disable(host->clk); in davinci_mmcsd_suspend()
1375 ret = clk_enable(host->clk); in davinci_mmcsd_resume()
1410 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");