Lines Matching refs:dest
29 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ argument
31 pci_read_config_word(dev, vsec + 0x6, dest); \
32 *dest >>= 4; \
34 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ argument
35 pci_read_config_byte(dev, vsec + 0x8, dest)
37 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ argument
38 pci_read_config_byte(dev, vsec + 0x9, dest)
50 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ argument
51 pci_read_config_byte(dev, vsec + 0xa, dest)
60 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ argument
61 pci_read_config_word(dev, vsec + 0xc, dest)
62 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ argument
63 pci_read_config_byte(dev, vsec + 0xe, dest)
64 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ argument
65 pci_read_config_byte(dev, vsec + 0xf, dest)
66 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ argument
67 pci_read_config_word(dev, vsec + 0x10, dest)
69 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ argument
70 pci_read_config_byte(dev, vsec + 0x13, dest)
77 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ argument
78 pci_read_config_dword(dev, vsec + 0x20, dest)
79 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ argument
80 pci_read_config_dword(dev, vsec + 0x24, dest)
81 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ argument
82 pci_read_config_dword(dev, vsec + 0x28, dest)
83 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ argument
84 pci_read_config_dword(dev, vsec + 0x2c, dest)