Lines Matching refs:dev
29 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ argument
31 pci_read_config_word(dev, vsec + 0x6, dest); \
34 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ argument
35 pci_read_config_byte(dev, vsec + 0x8, dest)
37 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ argument
38 pci_read_config_byte(dev, vsec + 0x9, dest)
50 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ argument
51 pci_read_config_byte(dev, vsec + 0xa, dest)
52 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ argument
53 pci_write_config_byte(dev, vsec + 0xa, val)
60 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ argument
61 pci_read_config_word(dev, vsec + 0xc, dest)
62 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ argument
63 pci_read_config_byte(dev, vsec + 0xe, dest)
64 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ argument
65 pci_read_config_byte(dev, vsec + 0xf, dest)
66 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ argument
67 pci_read_config_word(dev, vsec + 0x10, dest)
69 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ argument
70 pci_read_config_byte(dev, vsec + 0x13, dest)
71 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ argument
72 pci_write_config_byte(dev, vsec + 0x13, val)
77 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ argument
78 pci_read_config_dword(dev, vsec + 0x20, dest)
79 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ argument
80 pci_read_config_dword(dev, vsec + 0x24, dest)
81 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ argument
82 pci_read_config_dword(dev, vsec + 0x28, dest)
83 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ argument
84 pci_read_config_dword(dev, vsec + 0x2c, dest)
131 static inline resource_size_t p1_base(struct pci_dev *dev) in p1_base() argument
133 return pci_resource_start(dev, 2); in p1_base()
136 static inline resource_size_t p1_size(struct pci_dev *dev) in p1_size() argument
138 return pci_resource_len(dev, 2); in p1_size()
141 static inline resource_size_t p2_base(struct pci_dev *dev) in p2_base() argument
143 return pci_resource_start(dev, 0); in p2_base()
146 static inline resource_size_t p2_size(struct pci_dev *dev) in p2_size() argument
148 return pci_resource_len(dev, 0); in p2_size()
151 static int find_cxl_vsec(struct pci_dev *dev) in find_cxl_vsec() argument
153 return pci_find_vsec_capability(dev, PCI_VENDOR_ID_IBM, CXL_PCI_VSEC_ID); in find_cxl_vsec()
156 static void dump_cxl_config_space(struct pci_dev *dev) in dump_cxl_config_space() argument
161 dev_info(&dev->dev, "dump_cxl_config_space\n"); in dump_cxl_config_space()
163 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); in dump_cxl_config_space()
164 dev_info(&dev->dev, "BAR0: %#.8x\n", val); in dump_cxl_config_space()
165 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); in dump_cxl_config_space()
166 dev_info(&dev->dev, "BAR1: %#.8x\n", val); in dump_cxl_config_space()
167 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); in dump_cxl_config_space()
168 dev_info(&dev->dev, "BAR2: %#.8x\n", val); in dump_cxl_config_space()
169 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); in dump_cxl_config_space()
170 dev_info(&dev->dev, "BAR3: %#.8x\n", val); in dump_cxl_config_space()
171 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); in dump_cxl_config_space()
172 dev_info(&dev->dev, "BAR4: %#.8x\n", val); in dump_cxl_config_space()
173 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); in dump_cxl_config_space()
174 dev_info(&dev->dev, "BAR5: %#.8x\n", val); in dump_cxl_config_space()
176 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", in dump_cxl_config_space()
177 p1_base(dev), p1_size(dev)); in dump_cxl_config_space()
178 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", in dump_cxl_config_space()
179 p2_base(dev), p2_size(dev)); in dump_cxl_config_space()
180 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", in dump_cxl_config_space()
181 pci_resource_start(dev, 4), pci_resource_len(dev, 4)); in dump_cxl_config_space()
183 if (!(vsec = find_cxl_vsec(dev))) in dump_cxl_config_space()
187 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) in dump_cxl_config_space()
189 pci_read_config_dword(dev, vsec + 0x0, &val); in dump_cxl_config_space()
193 pci_read_config_dword(dev, vsec + 0x4, &val); in dump_cxl_config_space()
197 pci_read_config_dword(dev, vsec + 0x8, &val); in dump_cxl_config_space()
202 pci_read_config_dword(dev, vsec + 0xc, &val); in dump_cxl_config_space()
205 pci_read_config_dword(dev, vsec + 0x10, &val); in dump_cxl_config_space()
212 pci_read_config_dword(dev, vsec + 0x14, &val); in dump_cxl_config_space()
214 pci_read_config_dword(dev, vsec + 0x18, &val); in dump_cxl_config_space()
216 pci_read_config_dword(dev, vsec + 0x1c, &val); in dump_cxl_config_space()
219 pci_read_config_dword(dev, vsec + 0x20, &val); in dump_cxl_config_space()
221 pci_read_config_dword(dev, vsec + 0x24, &val); in dump_cxl_config_space()
223 pci_read_config_dword(dev, vsec + 0x28, &val); in dump_cxl_config_space()
225 pci_read_config_dword(dev, vsec + 0x2c, &val); in dump_cxl_config_space()
228 pci_read_config_dword(dev, vsec + 0x30, &val); in dump_cxl_config_space()
230 pci_read_config_dword(dev, vsec + 0x34, &val); in dump_cxl_config_space()
232 pci_read_config_dword(dev, vsec + 0x38, &val); in dump_cxl_config_space()
234 pci_read_config_dword(dev, vsec + 0x3c, &val); in dump_cxl_config_space()
237 pci_read_config_dword(dev, vsec + 0x40, &val); in dump_cxl_config_space()
239 pci_read_config_dword(dev, vsec + 0x44, &val); in dump_cxl_config_space()
242 pci_read_config_dword(dev, vsec + 0x48, &val); in dump_cxl_config_space()
244 pci_read_config_dword(dev, vsec + 0x4c, &val); in dump_cxl_config_space()
247 pci_read_config_dword(dev, vsec + 0x50, &val); in dump_cxl_config_space()
249 pci_read_config_dword(dev, vsec + 0x54, &val); in dump_cxl_config_space()
251 pci_read_config_dword(dev, vsec + 0x58, &val); in dump_cxl_config_space()
253 pci_read_config_dword(dev, vsec + 0x58, &val); in dump_cxl_config_space()
265 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) in dump_afu_descriptor()
361 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid, in cxl_calc_capp_routing() argument
368 if (!(np = pnv_pci_get_phb_node(dev))) in cxl_calc_capp_routing()
398 static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind, in get_phb_indications() argument
407 if (!(np = pnv_pci_get_phb_node(dev))) { in get_phb_indications()
431 int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg) in cxl_get_xsl9_dsnctl() argument
441 if (get_phb_indications(dev, &capiind, &asnind, &nbwind)) in cxl_get_xsl9_dsnctl()
475 struct pci_dev *dev) in init_implementation_adapter_regs_psl9() argument
484 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id); in init_implementation_adapter_regs_psl9()
488 rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl); in init_implementation_adapter_regs_psl9()
535 dev_dbg(&dev->dev, "No data-cache present\n"); in init_implementation_adapter_regs_psl9()
542 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev) in init_implementation_adapter_regs_psl8() argument
550 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id); in init_implementation_adapter_regs_psl8()
597 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev) in cxl_setup_psl_timebase() argument
603 if (!(np = pnv_pci_get_phb_node(dev))) in cxl_setup_psl_timebase()
610 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n"); in cxl_setup_psl_timebase()
650 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_setup_irq() local
652 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); in cxl_pci_setup_irq()
657 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_update_image_control() local
662 if (!(vsec = find_cxl_vsec(dev))) { in cxl_update_image_control()
663 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); in cxl_update_image_control()
667 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) { in cxl_update_image_control()
668 dev_err(&dev->dev, "failed to read image state: %i\n", rc); in cxl_update_image_control()
682 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) { in cxl_update_image_control()
683 dev_err(&dev->dev, "failed to update image control: %i\n", rc); in cxl_update_image_control()
692 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_alloc_one_irq() local
694 return pnv_cxl_alloc_hwirqs(dev, 1); in cxl_pci_alloc_one_irq()
699 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_release_one_irq() local
701 return pnv_cxl_release_hwirqs(dev, hwirq, 1); in cxl_pci_release_one_irq()
707 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_alloc_irq_ranges() local
709 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); in cxl_pci_alloc_irq_ranges()
715 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_release_irq_ranges() local
717 pnv_cxl_release_hwirq_ranges(irqs, dev); in cxl_pci_release_irq_ranges()
720 static int setup_cxl_bars(struct pci_dev *dev) in setup_cxl_bars() argument
723 if ((p1_base(dev) < 0x100000000ULL) || in setup_cxl_bars()
724 (p2_base(dev) < 0x100000000ULL)) { in setup_cxl_bars()
725 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); in setup_cxl_bars()
734 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); in setup_cxl_bars()
735 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); in setup_cxl_bars()
741 static int switch_card_to_cxl(struct pci_dev *dev) in switch_card_to_cxl() argument
747 dev_info(&dev->dev, "switch card to CXL\n"); in switch_card_to_cxl()
749 if (!(vsec = find_cxl_vsec(dev))) { in switch_card_to_cxl()
750 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); in switch_card_to_cxl()
754 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) { in switch_card_to_cxl()
755 dev_err(&dev->dev, "failed to read current mode control: %i", rc); in switch_card_to_cxl()
760 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) { in switch_card_to_cxl()
761 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc); in switch_card_to_cxl()
774 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) in pci_map_slice_regs() argument
780 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); in pci_map_slice_regs()
781 p2n_base = p2_base(dev) + (afu->slice * p2n_size); in pci_map_slice_regs()
782 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size)); in pci_map_slice_regs()
783 …afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_… in pci_map_slice_regs()
800 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); in pci_map_slice_regs()
820 void cxl_pci_release_afu(struct device *dev) in cxl_pci_release_afu() argument
822 struct cxl_afu *afu = to_cxl_afu(dev); in cxl_pci_release_afu()
867 dev_warn(&afu->dev, in cxl_read_afu_descriptor()
870 dev_info(&afu->dev, in cxl_read_afu_descriptor()
886 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); in cxl_afu_descriptor_looks_ok()
891 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size); in cxl_afu_descriptor_looks_ok()
896 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); in cxl_afu_descriptor_looks_ok()
912 dev_err(&afu->dev, "AFU does not support any processes\n"); in cxl_afu_descriptor_looks_ok()
930 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); in sanitise_afu_regs_psl9()
942 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); in sanitise_afu_regs_psl9()
952 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); in sanitise_afu_regs_psl9()
958 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); in sanitise_afu_regs_psl9()
976 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); in sanitise_afu_regs_psl8()
997 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); in sanitise_afu_regs_psl8()
1007 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); in sanitise_afu_regs_psl8()
1013 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); in sanitise_afu_regs_psl8()
1064 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) in pci_configure_afu() argument
1068 if ((rc = pci_map_slice_regs(afu, adapter, dev))) in pci_configure_afu()
1128 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) in pci_init_afu() argument
1143 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); in pci_init_afu()
1147 rc = pci_configure_afu(afu, adapter, dev); in pci_init_afu()
1167 dev_info(&afu->dev, "Can't register vPHB\n"); in pci_init_afu()
1172 device_del(&afu->dev); in pci_init_afu()
1176 put_device(&afu->dev); in pci_init_afu()
1206 device_unregister(&afu->dev); in cxl_pci_remove_afu()
1211 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_reset() local
1215 dev_warn(&dev->dev, in cxl_pci_reset()
1220 dev_info(&dev->dev, "CXL reset\n"); in cxl_pci_reset()
1230 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) { in cxl_pci_reset()
1231 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); in cxl_pci_reset()
1238 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) in cxl_map_adapter_regs() argument
1240 if (pci_request_region(dev, 2, "priv 2 regs")) in cxl_map_adapter_regs()
1242 if (pci_request_region(dev, 0, "priv 1 regs")) in cxl_map_adapter_regs()
1246 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); in cxl_map_adapter_regs()
1248 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) in cxl_map_adapter_regs()
1251 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) in cxl_map_adapter_regs()
1260 pci_release_region(dev, 0); in cxl_map_adapter_regs()
1262 pci_release_region(dev, 2); in cxl_map_adapter_regs()
1272 pci_release_region(to_pci_dev(adapter->dev.parent), 2); in cxl_unmap_adapter_regs()
1277 pci_release_region(to_pci_dev(adapter->dev.parent), 0); in cxl_unmap_adapter_regs()
1281 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) in cxl_read_vsec() argument
1289 if (!(vsec = find_cxl_vsec(dev))) { in cxl_read_vsec()
1290 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); in cxl_read_vsec()
1294 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); in cxl_read_vsec()
1296 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n"); in cxl_read_vsec()
1300 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); in cxl_read_vsec()
1301 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); in cxl_read_vsec()
1302 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); in cxl_read_vsec()
1303 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); in cxl_read_vsec()
1304 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); in cxl_read_vsec()
1305 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); in cxl_read_vsec()
1310 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); in cxl_read_vsec()
1311 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); in cxl_read_vsec()
1312 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); in cxl_read_vsec()
1313 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); in cxl_read_vsec()
1314 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); in cxl_read_vsec()
1324 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; in cxl_read_vsec()
1337 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev) in cxl_fixup_malformed_tlp() argument
1344 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))) in cxl_fixup_malformed_tlp()
1346 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data); in cxl_fixup_malformed_tlp()
1352 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data); in cxl_fixup_malformed_tlp()
1366 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) in cxl_vsec_looks_ok() argument
1372 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n"); in cxl_vsec_looks_ok()
1377 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n", in cxl_vsec_looks_ok()
1385 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n"); in cxl_vsec_looks_ok()
1390 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n"); in cxl_vsec_looks_ok()
1394 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) { in cxl_vsec_looks_ok()
1395 dev_err(&dev->dev, "ABORTING: Problem state size larger than " in cxl_vsec_looks_ok()
1397 adapter->ps_size, p2_size(dev) - adapter->native->ps_off); in cxl_vsec_looks_ok()
1406 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf); in cxl_pci_read_adapter_vpd()
1409 static void cxl_release_adapter(struct device *dev) in cxl_release_adapter() argument
1411 struct cxl *adapter = to_cxl_adapter(dev); in cxl_release_adapter()
1443 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev) in cxl_configure_adapter() argument
1447 adapter->dev.parent = &dev->dev; in cxl_configure_adapter()
1448 adapter->dev.release = cxl_release_adapter; in cxl_configure_adapter()
1449 pci_set_drvdata(dev, adapter); in cxl_configure_adapter()
1451 rc = pci_enable_device(dev); in cxl_configure_adapter()
1453 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); in cxl_configure_adapter()
1457 if ((rc = cxl_read_vsec(adapter, dev))) in cxl_configure_adapter()
1460 if ((rc = cxl_vsec_looks_ok(adapter, dev))) in cxl_configure_adapter()
1463 cxl_fixup_malformed_tlp(adapter, dev); in cxl_configure_adapter()
1465 if ((rc = setup_cxl_bars(dev))) in cxl_configure_adapter()
1468 if ((rc = switch_card_to_cxl(dev))) in cxl_configure_adapter()
1474 if ((rc = cxl_map_adapter_regs(adapter, dev))) in cxl_configure_adapter()
1480 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev))) in cxl_configure_adapter()
1484 pci_set_master(dev); in cxl_configure_adapter()
1489 if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1)) in cxl_configure_adapter()
1490 dev_info(&dev->dev, "Tunneled operations unsupported\n"); in cxl_configure_adapter()
1495 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode))) in cxl_configure_adapter()
1500 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) in cxl_configure_adapter()
1504 cxl_setup_psl_timebase(adapter, dev); in cxl_configure_adapter()
1519 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); in cxl_deconfigure_adapter()
1534 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_stop_trace_psl9() local
1541 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n", in cxl_stop_trace_psl9()
1615 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev) in set_sl_ops() argument
1618 dev_info(&dev->dev, "Device uses a PSL8\n"); in set_sl_ops()
1621 dev_info(&dev->dev, "Device uses a PSL9\n"); in set_sl_ops()
1627 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev) in cxl_pci_init_adapter() argument
1642 set_sl_ops(adapter, dev); in cxl_pci_init_adapter()
1650 rc = cxl_configure_adapter(adapter, dev); in cxl_pci_init_adapter()
1652 pci_disable_device(dev); in cxl_pci_init_adapter()
1675 device_del(&adapter->dev); in cxl_pci_init_adapter()
1682 put_device(&adapter->dev); in cxl_pci_init_adapter()
1686 cxl_release_adapter(&adapter->dev); in cxl_pci_init_adapter()
1704 device_unregister(&adapter->dev); in cxl_pci_remove_adapter()
1709 int cxl_slot_is_switched(struct pci_dev *dev) in cxl_slot_is_switched() argument
1714 if (!(np = pci_device_to_OF_node(dev))) { in cxl_slot_is_switched()
1729 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) in cxl_probe() argument
1735 if (cxl_pci_is_vphb_device(dev)) { in cxl_probe()
1736 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n"); in cxl_probe()
1740 if (cxl_slot_is_switched(dev)) { in cxl_probe()
1741 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n"); in cxl_probe()
1746 dev_info(&dev->dev, "Only Radix mode supported\n"); in cxl_probe()
1751 dump_cxl_config_space(dev); in cxl_probe()
1753 adapter = cxl_pci_init_adapter(dev); in cxl_probe()
1755 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); in cxl_probe()
1760 if ((rc = pci_init_afu(adapter, slice, dev))) { in cxl_probe()
1761 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); in cxl_probe()
1767 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc); in cxl_probe()
1773 static void cxl_remove(struct pci_dev *dev) in cxl_remove() argument
1775 struct cxl *adapter = pci_get_drvdata(dev); in cxl_remove()
1806 afu_drv = to_pci_driver(afu_dev->dev.driver); in cxl_vphb_error_detected()
1880 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n"); in cxl_pci_error_detected()
1960 dev_warn(&adapter->dev, in cxl_pci_error_detected()
2020 afu_dev->dev.archdata.cxl_ctx = ctx; in cxl_pci_slot_reset()
2033 afu_drv = to_pci_driver(afu_dev->dev.driver); in cxl_pci_slot_reset()
2057 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n"); in cxl_pci_slot_reset()
2082 afu_drv = to_pci_driver(afu_dev->dev.driver); in cxl_pci_resume()