Lines Matching +full:gemini +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0-only
3 * lpc_ich.c - LPC interface for Intel ICH
7 * Power Management, System Management, GPIO, RTC, and LPC
12 * Copyright (c) 2017, 2021-2022 Intel Corporation
14 * Author: Aaron Sierra <asierra@xes-inc.com>
18 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
19 * document number 290687-002, 298242-027: 82801BA (ICH2)
20 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
21 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
22 * document number 290744-001, 290745-025: 82801DB (ICH4)
23 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
24 * document number 273599-001, 273645-002: 82801E (C-ICH)
25 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
26 * document number 300641-004, 300884-013: 6300ESB
27 * document number 301473-002, 301474-026: 82801F (ICH6)
28 * document number 313082-001, 313075-006: 631xESB, 632xESB
29 * document number 307013-003, 307014-024: 82801G (ICH7)
30 * document number 322896-001, 322897-001: NM10
31 * document number 313056-003, 313057-017: 82801H (ICH8)
32 * document number 316972-004, 316973-012: 82801I (ICH9)
33 * document number 319973-002, 319974-002: 82801J (ICH10)
34 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
35 * document number 320066-003, 320257-008: EP80597 (IICH)
36 * document number 324645-001, 324646-001: Cougar Point (CPT)
102 /* ACPI - TCO */
106 /* ACPI - SMI */
121 /* ACPI - GPE0 */
186 .name = "apollolake-pinctrl",
193 .name = "apollolake-pinctrl",
200 .name = "apollolake-pinctrl",
207 .name = "apollolake-pinctrl",
216 .name = "intel-spi",
227 LPC_ICH2M, /* ICH2-M */
228 LPC_ICH3, /* ICH3-S */
229 LPC_ICH3M, /* ICH3-M */
231 LPC_ICH4M, /* ICH4-M */
232 LPC_CICH, /* C-ICH */
236 LPC_ICH6M, /* ICH6-M */
241 LPC_ICH7M, /* ICH7-M & ICH7-U */
242 LPC_ICH7MDH, /* ICH7-M DH */
248 LPC_ICH8ME, /* ICH8M-E */
254 LPC_ICH9ME, /* ICH9M-E */
282 LPC_LPT_LP, /* Lynx Point-LP */
287 LPC_WPT_LP, /* Wildcat Point-LP */
292 LPC_GLK, /* Gemini Lake SoC */
310 .name = "ICH2-M",
314 .name = "ICH3-S",
318 .name = "ICH3-M",
326 .name = "ICH4-M",
330 .name = "C-ICH",
347 .name = "ICH6-M",
372 .name = "ICH7-M or ICH7-U",
377 .name = "ICH7-M DH",
407 .name = "ICH8M-E",
437 .name = "ICH9M-E",
624 .name = "Gemini Lake SoC",
884 if (priv->abase_save >= 0) { in lpc_ich_restore_config_space()
885 pci_write_config_byte(dev, priv->abase, priv->abase_save); in lpc_ich_restore_config_space()
886 priv->abase_save = -1; in lpc_ich_restore_config_space()
889 if (priv->actrl_pbase_save >= 0) { in lpc_ich_restore_config_space()
890 pci_write_config_byte(dev, priv->actrl_pbase, in lpc_ich_restore_config_space()
891 priv->actrl_pbase_save); in lpc_ich_restore_config_space()
892 priv->actrl_pbase_save = -1; in lpc_ich_restore_config_space()
895 if (priv->gctrl_save >= 0) { in lpc_ich_restore_config_space()
896 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); in lpc_ich_restore_config_space()
897 priv->gctrl_save = -1; in lpc_ich_restore_config_space()
906 switch (lpc_chipset_info[priv->chipset].iTCO_version) { in lpc_ich_enable_acpi_space()
912 pci_read_config_byte(dev, priv->abase, ®_save); in lpc_ich_enable_acpi_space()
913 pci_write_config_byte(dev, priv->abase, reg_save | 0x2); in lpc_ich_enable_acpi_space()
914 priv->abase_save = reg_save; in lpc_ich_enable_acpi_space()
921 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); in lpc_ich_enable_acpi_space()
922 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); in lpc_ich_enable_acpi_space()
923 priv->actrl_pbase_save = reg_save; in lpc_ich_enable_acpi_space()
933 pci_read_config_byte(dev, priv->gctrl, ®_save); in lpc_ich_enable_gpio_space()
934 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); in lpc_ich_enable_gpio_space()
935 priv->gctrl_save = reg_save; in lpc_ich_enable_gpio_space()
943 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); in lpc_ich_enable_pmc_space()
944 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); in lpc_ich_enable_pmc_space()
946 priv->actrl_pbase_save = reg_save; in lpc_ich_enable_pmc_space()
956 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); in lpc_ich_finalize_wdt_cell()
958 return -ENOMEM; in lpc_ich_finalize_wdt_cell()
960 info = &lpc_chipset_info[priv->chipset]; in lpc_ich_finalize_wdt_cell()
962 pdata->version = info->iTCO_version; in lpc_ich_finalize_wdt_cell()
963 strscpy(pdata->name, info->name, sizeof(pdata->name)); in lpc_ich_finalize_wdt_cell()
965 cell->platform_data = pdata; in lpc_ich_finalize_wdt_cell()
966 cell->pdata_size = sizeof(*pdata); in lpc_ich_finalize_wdt_cell()
975 cell->platform_data = &lpc_chipset_info[priv->chipset]; in lpc_ich_finalize_gpio_cell()
976 cell->pdata_size = sizeof(struct lpc_ich_info); in lpc_ich_finalize_gpio_cell()
990 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) in lpc_ich_check_conflict_gpio()
993 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) in lpc_ich_check_conflict_gpio()
996 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); in lpc_ich_check_conflict_gpio()
1013 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); in lpc_ich_init_gpio()
1016 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); in lpc_ich_init_gpio()
1017 lpc_ich_gpio_cell.num_resources--; in lpc_ich_init_gpio()
1022 res->start = base_addr + ACPIBASE_GPE_OFF; in lpc_ich_init_gpio()
1023 res->end = base_addr + ACPIBASE_GPE_END; in lpc_ich_init_gpio()
1031 lpc_ich_gpio_cell.num_resources--; in lpc_ich_init_gpio()
1039 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); in lpc_ich_init_gpio()
1042 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); in lpc_ich_init_gpio()
1043 ret = -ENODEV; in lpc_ich_init_gpio()
1049 res->start = base_addr; in lpc_ich_init_gpio()
1050 switch (lpc_chipset_info[priv->chipset].gpio_version) { in lpc_ich_init_gpio()
1053 res->end = res->start + 128 - 1; in lpc_ich_init_gpio()
1056 res->end = res->start + 64 - 1; in lpc_ich_init_gpio()
1066 lpc_chipset_info[priv->chipset].use_gpio = ret; in lpc_ich_init_gpio()
1070 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, in lpc_ich_init_gpio()
1090 return -ENODEV; in lpc_ich_init_wdt()
1093 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); in lpc_ich_init_wdt()
1096 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); in lpc_ich_init_wdt()
1097 ret = -ENODEV; in lpc_ich_init_wdt()
1102 res->start = base_addr + ACPIBASE_TCO_OFF; in lpc_ich_init_wdt()
1103 res->end = base_addr + ACPIBASE_TCO_END; in lpc_ich_init_wdt()
1106 res->start = base_addr + ACPIBASE_SMI_OFF; in lpc_ich_init_wdt()
1107 res->end = base_addr + ACPIBASE_SMI_END; in lpc_ich_init_wdt()
1113 * Get the Memory-Mapped GCS register. To get access to it in lpc_ich_init_wdt()
1122 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { in lpc_ich_init_wdt()
1124 lpc_ich_wdt_cell.num_resources--; in lpc_ich_init_wdt()
1125 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { in lpc_ich_init_wdt()
1129 dev_notice(&dev->dev, "RCBA is disabled by " in lpc_ich_init_wdt()
1131 ret = -ENODEV; in lpc_ich_init_wdt()
1135 res->start = base_addr + ACPIBASE_GCS_OFF; in lpc_ich_init_wdt()
1136 res->end = base_addr + ACPIBASE_GCS_END; in lpc_ich_init_wdt()
1137 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { in lpc_ich_init_wdt()
1143 res->start = base_addr + ACPIBASE_PMC_OFF; in lpc_ich_init_wdt()
1144 res->end = base_addr + ACPIBASE_PMC_END; in lpc_ich_init_wdt()
1151 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, in lpc_ich_init_wdt()
1165 if (acpi_dev_present("INT3452", NULL, -1)) in lpc_ich_init_pinctrl()
1166 return -EEXIST; in lpc_ich_init_pinctrl()
1168 ret = p2sb_bar(dev->bus, 0, &base); in lpc_ich_init_pinctrl()
1177 mem->start = base.start + offset; in lpc_ich_init_pinctrl()
1178 mem->end = base.start + offset + APL_GPIO_RESOURCE_SIZE - 1; in lpc_ich_init_pinctrl()
1179 mem->flags = base.flags; in lpc_ich_init_pinctrl()
1182 return mfd_add_devices(&dev->dev, 0, apl_gpio_devices, in lpc_ich_init_pinctrl()
1218 return lpc_ich_set_writeable(pdev->bus, pdev->devfn); in lpc_ich_lpt_set_writeable()
1225 return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2)); in lpc_ich_bxt_set_writeable()
1236 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); in lpc_ich_init_spi()
1238 return -ENOMEM; in lpc_ich_init_spi()
1240 info->type = lpc_chipset_info[priv->chipset].spi_type; in lpc_ich_init_spi()
1242 switch (info->type) { in lpc_ich_init_spi()
1246 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1); in lpc_ich_init_spi()
1247 res->end = res->start + SPIBASE_BYT_SZ - 1; in lpc_ich_init_spi()
1249 info->set_writeable = lpc_ich_byt_set_writeable; in lpc_ich_init_spi()
1257 res->start = spi_base + SPIBASE_LPT; in lpc_ich_init_spi()
1258 res->end = res->start + SPIBASE_LPT_SZ - 1; in lpc_ich_init_spi()
1260 info->set_writeable = lpc_ich_lpt_set_writeable; in lpc_ich_init_spi()
1261 info->data = dev; in lpc_ich_init_spi()
1271 ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res); in lpc_ich_init_spi()
1275 info->set_writeable = lpc_ich_bxt_set_writeable; in lpc_ich_init_spi()
1276 info->data = dev; in lpc_ich_init_spi()
1280 return -EINVAL; in lpc_ich_init_spi()
1283 if (!res->start) in lpc_ich_init_spi()
1284 return -ENODEV; in lpc_ich_init_spi()
1289 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE, in lpc_ich_init_spi()
1300 priv = devm_kzalloc(&dev->dev, in lpc_ich_probe()
1303 return -ENOMEM; in lpc_ich_probe()
1305 priv->chipset = id->driver_data; in lpc_ich_probe()
1307 priv->actrl_pbase_save = -1; in lpc_ich_probe()
1308 priv->abase_save = -1; in lpc_ich_probe()
1310 priv->abase = ACPIBASE; in lpc_ich_probe()
1311 priv->actrl_pbase = ACPICTRL_PMCBASE; in lpc_ich_probe()
1313 priv->gctrl_save = -1; in lpc_ich_probe()
1314 if (priv->chipset <= LPC_ICH5) { in lpc_ich_probe()
1315 priv->gbase = GPIOBASE_ICH0; in lpc_ich_probe()
1316 priv->gctrl = GPIOCTRL_ICH0; in lpc_ich_probe()
1318 priv->gbase = GPIOBASE_ICH6; in lpc_ich_probe()
1319 priv->gctrl = GPIOCTRL_ICH6; in lpc_ich_probe()
1324 if (lpc_chipset_info[priv->chipset].iTCO_version) { in lpc_ich_probe()
1330 if (lpc_chipset_info[priv->chipset].gpio_version) { in lpc_ich_probe()
1336 if (priv->chipset == LPC_APL) { in lpc_ich_probe()
1342 if (lpc_chipset_info[priv->chipset].spi_type) { in lpc_ich_probe()
1353 dev_warn(&dev->dev, "No MFD cells added\n"); in lpc_ich_probe()
1355 return -ENODEV; in lpc_ich_probe()
1363 mfd_remove_devices(&dev->dev); in lpc_ich_remove()
1376 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");