Lines Matching refs:TEGRA30_MC_RESET
1189 #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \ macro
1199 TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
1200 TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
1201 TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
1202 TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
1203 TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
1204 TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
1205 TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
1206 TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
1207 TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
1208 TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
1209 TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1210 TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
1211 TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
1212 TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
1213 TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
1214 TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
1215 TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
1216 TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),