Lines Matching +full:0 +full:x22c
37 .id = 0x00,
42 .reg = 0x34c,
43 .shift = 0,
44 .mask = 0xff,
45 .def = 0x0,
50 .id = 0x01,
55 .reg = 0x228,
59 .reg = 0x2e8,
60 .shift = 0,
61 .mask = 0xff,
62 .def = 0x4e,
67 .id = 0x02,
72 .reg = 0x228,
76 .reg = 0x2f4,
77 .shift = 0,
78 .mask = 0xff,
79 .def = 0x4e,
84 .id = 0x03,
89 .reg = 0x228,
93 .reg = 0x2e8,
95 .mask = 0xff,
96 .def = 0x4e,
101 .id = 0x04,
106 .reg = 0x228,
110 .reg = 0x2f4,
112 .mask = 0xff,
113 .def = 0x4e,
118 .id = 0x05,
123 .reg = 0x228,
127 .reg = 0x2ec,
128 .shift = 0,
129 .mask = 0xff,
130 .def = 0x4e,
135 .id = 0x06,
140 .reg = 0x228,
144 .reg = 0x2f8,
145 .shift = 0,
146 .mask = 0xff,
147 .def = 0x4e,
152 .id = 0x07,
157 .reg = 0x228,
161 .reg = 0x2ec,
163 .mask = 0xff,
164 .def = 0x4e,
169 .id = 0x08,
174 .reg = 0x228,
178 .reg = 0x2f8,
180 .mask = 0xff,
181 .def = 0x4e,
186 .id = 0x09,
191 .reg = 0x228,
195 .reg = 0x300,
196 .shift = 0,
197 .mask = 0xff,
198 .def = 0x17,
203 .id = 0x0a,
208 .reg = 0x228,
212 .reg = 0x308,
213 .shift = 0,
214 .mask = 0xff,
215 .def = 0x09,
220 .id = 0x0b,
225 .reg = 0x228,
229 .reg = 0x308,
231 .mask = 0xff,
232 .def = 0x09,
237 .id = 0x0c,
242 .reg = 0x228,
246 .reg = 0x328,
247 .shift = 0,
248 .mask = 0xff,
249 .def = 0x50,
254 .id = 0x0d,
259 .reg = 0x228,
263 .reg = 0x364,
264 .shift = 0,
265 .mask = 0xff,
266 .def = 0x2c,
271 .id = 0x0e,
276 .reg = 0x228,
280 .reg = 0x2e0,
281 .shift = 0,
282 .mask = 0xff,
283 .def = 0x10,
288 .id = 0x0f,
293 .reg = 0x228,
297 .reg = 0x2e4,
298 .shift = 0,
299 .mask = 0xff,
300 .def = 0x04,
305 .id = 0x10,
310 .reg = 0x228,
314 .reg = 0x2f0,
315 .shift = 0,
316 .mask = 0xff,
317 .def = 0xff,
322 .id = 0x11,
327 .reg = 0x228,
331 .reg = 0x2fc,
332 .shift = 0,
333 .mask = 0xff,
334 .def = 0xff,
339 .id = 0x12,
344 .reg = 0x228,
348 .reg = 0x334,
349 .shift = 0,
350 .mask = 0xff,
351 .def = 0x0a,
356 .id = 0x13,
361 .reg = 0x228,
365 .reg = 0x33c,
366 .shift = 0,
367 .mask = 0xff,
368 .def = 0x0a,
373 .id = 0x14,
378 .reg = 0x228,
382 .reg = 0x30c,
383 .shift = 0,
384 .mask = 0xff,
385 .def = 0x0a,
390 .id = 0x15,
395 .reg = 0x228,
399 .reg = 0x318,
400 .shift = 0,
401 .mask = 0xff,
402 .def = 0xff,
407 .id = 0x16,
412 .reg = 0x228,
416 .reg = 0x310,
417 .shift = 0,
418 .mask = 0xff,
419 .def = 0x05,
424 .id = 0x17,
429 .reg = 0x228,
433 .reg = 0x310,
435 .mask = 0xff,
436 .def = 0x50,
441 .id = 0x18,
446 .reg = 0x228,
450 .reg = 0x334,
452 .mask = 0xff,
453 .def = 0x13,
458 .id = 0x19,
463 .reg = 0x228,
467 .reg = 0x33c,
469 .mask = 0xff,
470 .def = 0x13,
475 .id = 0x1a,
480 .reg = 0x228,
484 .reg = 0x328,
486 .mask = 0xff,
487 .def = 0x80,
492 .id = 0x1b,
497 .reg = 0x228,
501 .reg = 0x32c,
502 .shift = 0,
503 .mask = 0xff,
504 .def = 0x42,
509 .id = 0x1c,
514 .reg = 0x228,
518 .reg = 0x32c,
520 .mask = 0xff,
521 .def = 0xff,
526 .id = 0x1d,
531 .reg = 0x228,
535 .reg = 0x344,
536 .shift = 0,
537 .mask = 0xff,
538 .def = 0x10,
543 .id = 0x1e,
548 .reg = 0x228,
552 .reg = 0x344,
554 .mask = 0xff,
555 .def = 0x12,
560 .id = 0x1f,
565 .reg = 0x228,
569 .reg = 0x350,
570 .shift = 0,
571 .mask = 0xff,
572 .def = 0x33,
577 .id = 0x20,
582 .reg = 0x22c,
583 .bit = 0,
586 .reg = 0x338,
587 .shift = 0,
588 .mask = 0xff,
589 .def = 0x13,
594 .id = 0x21,
599 .reg = 0x22c,
603 .reg = 0x340,
604 .shift = 0,
605 .mask = 0xff,
606 .def = 0x13,
611 .id = 0x22,
616 .reg = 0x22c,
620 .reg = 0x354,
621 .shift = 0,
622 .mask = 0xff,
623 .def = 0xff,
628 .id = 0x23,
633 .reg = 0x22c,
637 .reg = 0x354,
639 .mask = 0xff,
640 .def = 0xd0,
645 .id = 0x24,
650 .reg = 0x22c,
654 .reg = 0x358,
655 .shift = 0,
656 .mask = 0xff,
657 .def = 0x2a,
662 .id = 0x25,
667 .reg = 0x22c,
671 .reg = 0x358,
673 .mask = 0xff,
674 .def = 0x74,
679 .id = 0x26,
684 .reg = 0x324,
685 .shift = 0,
686 .mask = 0xff,
687 .def = 0x04,
692 .id = 0x27,
697 .reg = 0x320,
698 .shift = 0,
699 .mask = 0xff,
700 .def = 0x04,
705 .id = 0x28,
710 .reg = 0x22c,
714 .reg = 0x300,
716 .mask = 0xff,
717 .def = 0x6c,
722 .id = 0x29,
727 .reg = 0x22c,
731 .reg = 0x304,
732 .shift = 0,
733 .mask = 0xff,
734 .def = 0x6c,
739 .id = 0x2a,
744 .reg = 0x22c,
748 .reg = 0x304,
750 .mask = 0xff,
751 .def = 0x6c,
756 .id = 0x2b,
761 .reg = 0x22c,
765 .reg = 0x330,
766 .shift = 0,
767 .mask = 0xff,
768 .def = 0x13,
773 .id = 0x2c,
778 .reg = 0x22c,
782 .reg = 0x364,
784 .mask = 0xff,
785 .def = 0x12,
790 .id = 0x2d,
795 .reg = 0x22c,
799 .reg = 0x368,
800 .shift = 0,
801 .mask = 0xff,
802 .def = 0xb2,
807 .id = 0x2e,
812 .reg = 0x22c,
816 .reg = 0x368,
818 .mask = 0xff,
819 .def = 0xb2,
824 .id = 0x2f,
829 .reg = 0x22c,
833 .reg = 0x36c,
834 .shift = 0,
835 .mask = 0xff,
836 .def = 0x12,
841 .id = 0x30,
846 .reg = 0x22c,
850 .reg = 0x30c,
852 .mask = 0xff,
853 .def = 0x9,
858 .id = 0x31,
863 .reg = 0x22c,
867 .reg = 0x2e0,
869 .mask = 0xff,
870 .def = 0x0c,
875 .id = 0x32,
880 .reg = 0x22c,
884 .reg = 0x2e4,
886 .mask = 0xff,
887 .def = 0x0e,
892 .id = 0x33,
897 .reg = 0x22c,
901 .reg = 0x338,
903 .mask = 0xff,
904 .def = 0x0a,
909 .id = 0x34,
914 .reg = 0x22c,
918 .reg = 0x340,
920 .mask = 0xff,
921 .def = 0x0a,
926 .id = 0x35,
931 .reg = 0x22c,
935 .reg = 0x318,
937 .mask = 0xff,
938 .def = 0xff,
943 .id = 0x36,
948 .reg = 0x22c,
952 .reg = 0x314,
953 .shift = 0,
954 .mask = 0xff,
955 .def = 0x10,
960 .id = 0x37,
965 .reg = 0x22c,
969 .reg = 0x31c,
970 .shift = 0,
971 .mask = 0xff,
972 .def = 0xff,
977 .id = 0x38,
982 .reg = 0x324,
984 .mask = 0xff,
985 .def = 0x0e,
990 .id = 0x39,
995 .reg = 0x320,
997 .mask = 0xff,
998 .def = 0x0e,
1003 .id = 0x3a,
1008 .reg = 0x22c,
1012 .reg = 0x330,
1014 .mask = 0xff,
1015 .def = 0xff,
1020 .id = 0x3b,
1025 .reg = 0x22c,
1029 .reg = 0x348,
1030 .shift = 0,
1031 .mask = 0xff,
1032 .def = 0x10,
1037 .id = 0x3c,
1042 .reg = 0x22c,
1046 .reg = 0x348,
1048 .mask = 0xff,
1049 .def = 0x06,
1054 .id = 0x3d,
1059 .reg = 0x22c,
1063 .reg = 0x350,
1065 .mask = 0xff,
1066 .def = 0x33,
1071 .id = 0x3e,
1076 .reg = 0x22c,
1080 .reg = 0x35c,
1081 .shift = 0,
1082 .mask = 0xff,
1083 .def = 0xff,
1088 .id = 0x3f,
1093 .reg = 0x22c,
1097 .reg = 0x35c,
1099 .mask = 0xff,
1100 .def = 0xff,
1105 .id = 0x40,
1110 .reg = 0x230,
1111 .bit = 0,
1114 .reg = 0x360,
1115 .shift = 0,
1116 .mask = 0xff,
1117 .def = 0x42,
1122 .id = 0x41,
1127 .reg = 0x230,
1131 .reg = 0x360,
1133 .mask = 0xff,
1134 .def = 0x2a,
1142 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1143 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1144 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
1145 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
1146 { .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
1147 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1148 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1149 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1150 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1151 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
1152 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1153 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1154 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1155 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
1156 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
1157 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
1199 TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
1200 TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
1201 TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
1202 TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
1203 TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
1204 TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
1205 TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
1206 TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
1207 TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
1208 TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
1209 TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1210 TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
1211 TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
1212 TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
1213 TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
1214 TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
1215 TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
1216 TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),
1273 arb_nsec = 0; in tegra30_mc_tune_client_latency()
1306 return 0; in tegra30_mc_icc_set()
1313 return 0; in tegra30_mc_icc_set()
1331 return 0; in tegra30_mc_icc_aggreate()
1339 unsigned int i, idx = spec->args[0]; in tegra30_mc_of_icc_xlate_extended()
1371 for (i = 0; i < mc->soc->num_clients; i++) { in tegra30_mc_of_icc_xlate_extended()
1392 .client_id_mask = 0x7f,