357 	struct tegra_mc *mc;  member
503 	struct tegra_mc *mc = emc->mc;  in emc_prepare_mc_clk_cfg()  local
508 	for (i = 0; i < mc->num_timings; i++) {  in emc_prepare_mc_clk_cfg()
509 		if (mc->timings[i].rate != rate)  in emc_prepare_mc_clk_cfg()
512 		if (mc->timings[i].emem_data[misc0_index] & BIT(27))  in emc_prepare_mc_clk_cfg()
553 	emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);  in emc_prepare_timing_change()
574 	dram_num = tegra_mc_get_emem_device_count(emc->mc);  in emc_prepare_timing_change()
585 	val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ);  in emc_prepare_timing_change()
591 		mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ);  in emc_prepare_timing_change()
592 		mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);  in emc_prepare_timing_change()
596 		mc_writel(emc->mc,  in emc_prepare_timing_change()
643 	err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);  in emc_prepare_timing_change()
787 	mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);  in emc_prepare_timing_change()
809 	dram_num = tegra_mc_get_emem_device_count(emc->mc);  in emc_complete_timing_change()
838 	mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);  in emc_complete_timing_change()
958 	struct tegra_mc *mc = emc->mc;  in emc_check_mc_timings()  local
961 	if (emc->num_timings != mc->num_timings) {  in emc_check_mc_timings()
963 			emc->num_timings, mc->num_timings);  in emc_check_mc_timings()
967 	for (i = 0; i < mc->num_timings; i++) {  in emc_check_mc_timings()
968 		if (emc->timings[i].rate != mc->timings[i].rate) {  in emc_check_mc_timings()
971 				emc->timings[i].rate, mc->timings[i].rate);  in emc_check_mc_timings()
1526 	const struct tegra_mc_soc *soc = emc->mc->soc;  in tegra_emc_interconnect_init()
1631 	emc->mc = devm_tegra_memory_controller_get(&pdev->dev);  in tegra_emc_probe()
1632 	if (IS_ERR(emc->mc))  in tegra_emc_probe()
1633 		return PTR_ERR(emc->mc);  in tegra_emc_probe()