Lines Matching refs:TEGRA124_MC_RESET
1112 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \ macro
1122 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
1123 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
1124 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
1125 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
1126 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
1127 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
1128 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
1129 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
1130 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1131 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
1132 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
1133 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1134 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1135 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1136 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1137 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1138 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1139 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1140 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1141 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1142 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1143 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1144 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1145 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),