20 #define FMC2_BCR(x)			((x) * 0x8 + FMC2_BCR1)  macro
186 	ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_mux()
203 	ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_waitcfg()
220 	ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_sync_trans()
237 	ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_async_trans()
254 	ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_cpsize()
271 	ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_address_hold()
296 	ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_check_clk_period()
360 		*reg = FMC2_BCR(cs);  in stm32_fmc2_ebi_get_reg()
523 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr);  in stm32_fmc2_ebi_set_trans_type()
546 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val);  in stm32_fmc2_ebi_set_buswidth()
578 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);  in stm32_fmc2_ebi_set_cpsize()
591 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val);  in stm32_fmc2_ebi_set_bl_setup()
608 	ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_set_address_setup()
980 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs),  in stm32_fmc2_ebi_enable_bank()
986 	regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0);  in stm32_fmc2_ebi_disable_bank()
995 		ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]);  in stm32_fmc2_ebi_save_setup()
1010 		regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]);  in stm32_fmc2_ebi_set_setup()
1042 		ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);  in stm32_fmc2_ebi_nwait_used_by_ctrls()