Lines Matching refs:u32
107 u32 freq_hz;
108 u32 volt_uv;
165 u32 timings_arr_size;
166 u32 *timing_row;
167 u32 *timing_data;
168 u32 *timing_power;
171 u32 bypass_timing_row;
172 u32 bypass_timing_data;
173 u32 bypass_timing_power;
194 u32 __val; \
655 unsigned long *target_volt, u32 flags) in exynos5_dmc_get_volt_freq()
683 u32 flags) in exynos5_dmc_target()
763 u32 beg_value) in exynos5_dmc_start_perf_events()
842 u32 val; in exynos5_dmc_perf_events_check()
1036 static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row, in create_timings_aligned()
1037 u32 *reg_timing_data, u32 *reg_timing_power, in create_timings_aligned()
1038 u32 clk_period_ps) in create_timings_aligned()
1040 u32 val; in create_timings_aligned()
1180 u32 freq_mhz, clk_period_ps; in of_get_dram_timings()
1189 sizeof(u32), GFP_KERNEL); in of_get_dram_timings()
1196 sizeof(u32), GFP_KERNEL); in of_get_dram_timings()
1203 sizeof(u32), GFP_KERNEL); in of_get_dram_timings()