156 	void __iomem *base_drexi0;  member
387 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);  in exynos5_set_bypass_dram_timings()
390 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);  in exynos5_set_bypass_dram_timings()
394 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);  in exynos5_set_bypass_dram_timings()
398 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);  in exynos5_set_bypass_dram_timings()
427 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);  in exynos5_dram_change_timings()
430 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);  in exynos5_dram_change_timings()
434 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);  in exynos5_dram_change_timings()
438 	       dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);  in exynos5_dram_change_timings()
766 	writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);  in exynos5_dmc_start_perf_events()
770 	writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);  in exynos5_dmc_start_perf_events()
774 	writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);  in exynos5_dmc_start_perf_events()
778 	writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);  in exynos5_dmc_start_perf_events()
785 	writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);  in exynos5_dmc_start_perf_events()
789 	writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);  in exynos5_dmc_start_perf_events()
848 	writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);  in exynos5_dmc_perf_events_check()
852 	val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);  in exynos5_dmc_perf_events_check()
880 	writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);  in exynos5_dmc_enable_perf_events()
884 	writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);  in exynos5_dmc_enable_perf_events()
905 	writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);  in exynos5_dmc_disable_perf_events()
909 	writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);  in exynos5_dmc_disable_perf_events()
913 	writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);  in exynos5_dmc_disable_perf_events()
917 	writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);  in exynos5_dmc_disable_perf_events()
1437 	dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0);  in exynos5_dmc_probe()
1438 	if (IS_ERR(dmc->base_drexi0))  in exynos5_dmc_probe()
1439 		return PTR_ERR(dmc->base_drexi0);  in exynos5_dmc_probe()