1537 	ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/  in pvr2_upload_firmware2()
1541 	ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/  in pvr2_upload_firmware2()
1544 	ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/  in pvr2_upload_firmware2()
1545 	ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/  in pvr2_upload_firmware2()
1546 	ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/  in pvr2_upload_firmware2()
1547 	ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/  in pvr2_upload_firmware2()
1548 	ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/  in pvr2_upload_firmware2()
1549 	ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/  in pvr2_upload_firmware2()
1550 	ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/  in pvr2_upload_firmware2()
1551 	ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/  in pvr2_upload_firmware2()
1552 	ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/  in pvr2_upload_firmware2()
1628 	ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/  in pvr2_upload_firmware2()
1629 	ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/  in pvr2_upload_firmware2()
3885 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)  in pvr2_write_register()  function
5012 	return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);  in pvr2_hdw_gpio_chg_dir()
5032 	return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);  in pvr2_hdw_gpio_chg_out()