204 	u8 r12, r15, r17, r18, r3D, r82, r84, r89;  in mxl111sf_config_pin_mux_modes()  local
221 	ret = mxl111sf_read_reg(state, 0x82, &r82);  in mxl111sf_config_pin_mux_modes()
251 		r82 |= PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
253 		r82 |= PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
255 		r82 |= PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
257 		r82 |= PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
279 		r82 |= PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
281 		r82 |= PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
283 		r82 |= PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
285 		r82 |= PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
307 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
309 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
311 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
313 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
335 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
337 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
339 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
341 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
363 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
365 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
367 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
369 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
391 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
393 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
395 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
397 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
419 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
421 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
423 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
425 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
447 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
449 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
451 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
453 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
475 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
477 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
479 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
481 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
504 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
506 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
508 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
510 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
530 	ret = mxl111sf_write_reg(state, 0x82, r82);  in mxl111sf_config_pin_mux_modes()