media/rc/ite-cir.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
15 /* interrupt types */
34 	/* hw-specific operation function pointers; most of these must be
37 	/* get pending interrupt causes */
53 	/* enable tx FIFO space available interrupt */
56 	/* disable tx FIFO space available interrupt */
98 	/* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135  * frequency A = (H - L) / (H + L). We can use this in order to honor the
136  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
170  * Environment Control - Low Pin Count Input / Output
171  * (EC - LPC I/O)
177 #define IT87_IER	0x01	/* interrupt enable register */
185 #define IT87_IIR	0x07	/* interrupt identification register */
190 #define IT87_TLDLIE	0x01	/* transmitter low data interrupt enable */
191 #define IT87_RDAIE	0x02	/* receiver data available interrupt enable */
192 #define IT87_RFOIE	0x04	/* receiver FIFO overrun interrupt enable */
193 #define IT87_IEC	0x08	/* interrupt enable control */
202 #define IT87_HCFS	0x40	/* high-speed carrier frequency select */
212 					 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 					 * 0x30 -> 25 */
228 #define IT87_RXFTO	0x80	/* receiver FIFO time-out */
231 #define IT87_IP		0x01	/* interrupt pending */
232 #define IT87_II		0x06	/* interrupt identification mask */
233 #define IT87_II_NOINT	0x00	/* no interrupt */
244  * Embedded Controller
250  * the controller firmware in use, we are going to use the PNP ID in order to
259 #define IT85_C0IER	0x02	/* interrupt enable register */
260 #define IT85_C0IIR	0x03	/* interrupt identification register */
269 #define IT85_C0WCL	0x0d	/* wakeup code length register */
270 #define IT85_C0WCR	0x0e	/* wakeup code read/write register */
271 #define IT85_C0WPS	0x0f	/* wakeup power control/status register */
280 					 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 					 * 0x0c -> 25 */
286 #define IT85_TLDLIE	0x01	/* TX low data level interrupt enable */
287 #define IT85_RDAIE	0x02	/* RX data available interrupt enable */
288 #define IT85_RFOIE	0x04	/* RX FIFO overrun interrupt enable */
289 #define IT85_IEC	0x80	/* interrupt enable function control */
292 #define IT85_TLDLI	0x01	/* transmitter low data level interrupt */
293 #define IT85_RDAI	0x02	/* receiver data available interrupt */
294 #define IT85_RFOI	0x04	/* receiver FIFO overrun interrupt */
295 #define IT85_NIP	0x80	/* no interrupt pending */
329 #define IT85_RXFTO	0x80	/* receiver FIFO time-out */
332 #define IT85_WCL	0x3f	/* wakeup code length mask */
335 #define IT85_CIRPOSIE	0x01	/* power on/off status interrupt enable */
336 #define IT85_CIRPOIS	0x02	/* power on/off interrupt status */
337 #define IT85_CIRPOII	0x04	/* power on/off interrupt identification */
338 #define IT85_RCRST	0x10	/* wakeup code reading counter reset bit */
339 #define IT85_WCRST	0x20	/* wakeup code writing counter reset bit */
349  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350  * selectable by a single bank-select bit that's mapped onto both banks. The
353  * reserved high-order bit are placed at the same offset in both banks in
366 #define IT8708_C0IER	0x02	/* interrupt enable register */
367 #define IT8708_C0IIR	0x03	/* interrupt identification register */
382 #define IT8708_C0WCL	0x05	/* wakeup code length register */
383 #define IT8708_C0WCR	0x06	/* wakeup code read/write register */
384 #define IT8708_C0WPS	0x07	/* wakeup power control/status register */
408  * a specific firmware running on the IT8512's embedded micro-controller.
409  * In addition of the embedded micro-controller, the IT8512 chip contains a
412  * micro-controller. The CIR module is only accessible by the
413  * micro-controller.
415  * The battery-backed SRAM module is accessible by the host CPU and the
416  * micro-controller. So one of the MC's firmware role is to act as a bridge
420  * communication protocol is not, so it was reverse-engineered.
433 #define IT8709_IIR	0x1e	/* interrupt identification register */