media/rc/ite-cir.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 	/* hw-specific operation function pointers; most of these must be
92 	/* tx high carrier frequency, in Hz, 0 means no demodulation */
98 	/* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
133  * From two limit frequencies, L (low) and H (high), we can get both the
135  * frequency A = (H - L) / (H + L). We can use this in order to honor the
136  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
141 /* high speed carrier freq values */
170  * Environment Control - Low Pin Count Input / Output
171  * (EC - LPC I/O)
184 #define IT87_BDHR	0x06	/* baud rate divisor high byte register */
199 #define IT87_RXACT	0x08	/* receiver active */
202 #define IT87_HCFS	0x40	/* high-speed carrier frequency select */
212 					 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 					 * 0x30 -> 25 */
228 #define IT87_RXFTO	0x80	/* receiver FIFO time-out */
266 #define IT85_C0BDHR	0x09	/* baud rate divisor high byte register */
269 #define IT85_C0WCL	0x0d	/* wakeup code length register */
270 #define IT85_C0WCR	0x0e	/* wakeup code read/write register */
271 #define IT85_C0WPS	0x0f	/* wakeup power control/status register */
280 					 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 					 * 0x0c -> 25 */
299 #define IT85_HCFS	0x20	/* high speed carrier frequency select */
303 #define IT85_RXACT	0x08	/* receiver active */
329 #define IT85_RXFTO	0x80	/* receiver FIFO time-out */
332 #define IT85_WCL	0x3f	/* wakeup code length mask */
338 #define IT85_RCRST	0x10	/* wakeup code reading counter reset bit */
339 #define IT85_WCRST	0x20	/* wakeup code writing counter reset bit */
349  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350  * selectable by a single bank-select bit that's mapped onto both banks. The
353  * reserved high-order bit are placed at the same offset in both banks in
361 #define IT8708_HRAE	0x80	/* high registers access enable */
373 /* mapped onto the high bank */
375 #define IT8708_C0BDHR	0x02	/* baud rate divisor high byte register */
379  * in the hacked driver... most probably they belong to the high bank too,
382 #define IT8708_C0WCL	0x05	/* wakeup code length register */
383 #define IT8708_C0WCR	0x06	/* wakeup code read/write register */
384 #define IT8708_C0WPS	0x07	/* wakeup power control/status register */
408  * a specific firmware running on the IT8512's embedded micro-controller.
409  * In addition of the embedded micro-controller, the IT8512 chip contains a
412  * micro-controller. The CIR module is only accessible by the
413  * micro-controller.
415  * The battery-backed SRAM module is accessible by the host CPU and the
416  * micro-controller. So one of the MC's firmware role is to act as a bridge
420  * communication protocol is not, so it was reverse-engineered.