52 static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)  in ene_write_reg()  function
241 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,  in ene_rx_restore_hw_buffer()
243 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,  in ene_rx_restore_hw_buffer()
245 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);  in ene_rx_restore_hw_buffer()
247 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,  in ene_rx_restore_hw_buffer()
249 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,  in ene_rx_restore_hw_buffer()
251 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,  in ene_rx_restore_hw_buffer()
371 		ene_write_reg(dev, ENE_FAN_AS_IN1, 0);  in ene_rx_enable_fan_input()
373 		ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);  in ene_rx_enable_fan_input()
374 		ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);  in ene_rx_enable_fan_input()
389 	ene_write_reg(dev, ENE_CIRCFG2, 0x00);  in ene_rx_setup()
396 	ene_write_reg(dev, ENE_CIRRLC_CFG,  in ene_rx_setup()
419 		ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);  in ene_rx_setup()
470 		ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);  in ene_rx_enable_hw()
471 		ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);  in ene_rx_enable_hw()
477 		ene_write_reg(dev, ENE_IRQ, reg_value);  in ene_rx_enable_hw()
553 	ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);  in ene_tx_set_carrier()
554 	ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);  in ene_tx_set_carrier()
596 	ene_write_reg(dev, ENE_CIRCFG, conf1);  in ene_tx_enable()
602 	ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);  in ene_tx_disable()
652 	ene_write_reg(dev,  in ene_tx_sample()
698 	ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);  in ene_irq_status()
699 	ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);  in ene_irq_status()
704 		ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);  in ene_irq_status()
710 		ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);  in ene_irq_status()