Lines Matching refs:G1_REG_REF_PIC
32 { G1_REG_REF_PIC(2), 18, 0x3f },
33 { G1_REG_REF_PIC(2), 12, 0x3f },
34 { G1_REG_REF_PIC(2), 6, 0x3f },
35 { G1_REG_REF_PIC(2), 0, 0x3f },
40 { G1_REG_REF_PIC(0), 21, 0x7f },
41 { G1_REG_REF_PIC(0), 14, 0x7f },
42 { G1_REG_REF_PIC(0), 7, 0x7f },
43 { G1_REG_REF_PIC(0), 0, 0x7f },
48 { G1_REG_REF_PIC(1), 21, 0x7f },
49 { G1_REG_REF_PIC(1), 14, 0x7f },
50 { G1_REG_REF_PIC(1), 7, 0x7f },
51 { G1_REG_REF_PIC(1), 0, 0x7f },
56 { G1_REG_REF_PIC(3), 11, 0x7ff },
57 { G1_REG_REF_PIC(3), 0, 0x7ff },
64 { G1_REG_REF_PIC(3), 27, 0x1f },
65 { G1_REG_REF_PIC(3), 22, 0x1f },
85 { G1_REG_REF_PIC(4), 22, 0x3ff },
88 { G1_REG_REF_PIC(4), 12, 0x3ff },
89 { G1_REG_REF_PIC(4), 2, 0x3ff },
90 { G1_REG_REF_PIC(5), 22, 0x3ff },
91 { G1_REG_REF_PIC(5), 12, 0x3ff },
94 { G1_REG_REF_PIC(5), 2, 0x3ff },
95 { G1_REG_REF_PIC(6), 22, 0x3ff },
96 { G1_REG_REF_PIC(6), 12, 0x3ff },
97 { G1_REG_REF_PIC(6), 2, 0x3ff },
100 { G1_REG_REF_PIC(7), 22, 0x3ff },
101 { G1_REG_REF_PIC(7), 12, 0x3ff },
102 { G1_REG_REF_PIC(7), 2, 0x3ff },
161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()