Lines Matching refs:G1_SWREG
15 #define G1_SWREG(nr) ((nr) * 4) macro
17 #define G1_REG_RLC_VLC_BASE G1_SWREG(12)
18 #define G1_REG_DEC_OUT_BASE G1_SWREG(13)
19 #define G1_REG_REFER0_BASE G1_SWREG(14)
20 #define G1_REG_REFER1_BASE G1_SWREG(15)
21 #define G1_REG_REFER2_BASE G1_SWREG(16)
22 #define G1_REG_REFER3_BASE G1_SWREG(17)
23 #define G1_REG_QTABLE_BASE G1_SWREG(40)
181 vdpu_write_relaxed(vpu, reg, G1_SWREG(2)); in hantro_g1_mpeg2_dec_run()
194 vdpu_write_relaxed(vpu, reg, G1_SWREG(3)); in hantro_g1_mpeg2_dec_run()
200 vdpu_write_relaxed(vpu, reg, G1_SWREG(4)); in hantro_g1_mpeg2_dec_run()
208 vdpu_write_relaxed(vpu, reg, G1_SWREG(5)); in hantro_g1_mpeg2_dec_run()
212 vdpu_write_relaxed(vpu, reg, G1_SWREG(6)); in hantro_g1_mpeg2_dec_run()
221 vdpu_write_relaxed(vpu, reg, G1_SWREG(18)); in hantro_g1_mpeg2_dec_run()
225 vdpu_write_relaxed(vpu, reg, G1_SWREG(48)); in hantro_g1_mpeg2_dec_run()
228 vdpu_write_relaxed(vpu, reg, G1_SWREG(55)); in hantro_g1_mpeg2_dec_run()