platform/verisilicon/hantro.h

1 /* SPDX-License-Identifier: GPL-2.0 */
8  * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
19 #include <linux/reset.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-core.h>
26 #include <media/videobuf2-dma-contig.h>
45  * struct hantro_irq - irq handler and name
56  * struct hantro_variant - information about VPU hardware variant
64  * @postproc_fmts:		Post-processor formats.
65  * @num_postproc_fmts:		Number of post-processor formats.
66  * @postproc_ops:		Post-processor ops.
77  * @double_buffer:		core needs double buffering
107  * enum hantro_codec_mode - codec operating mode.
111  * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
118 	HANTRO_MODE_NONE = -1,
129  * struct hantro_ctrl - helper type to declare supported controls
139  * struct hantro_func - Hantro VPU functionality
174  * struct hantro_dev - driver data
184  * @resets:		Array of reset handles.
192  * @variant:		Hardware variant-specific parameters.
217  * struct hantro_ctx - Context (instance) private data.
232  * @jpeg_quality:	User-specified JPEG compression quality.
235  *			use the post-processor.
238  * @postproc:		Post-processing context.
239  * @h264_dec:		H.264-decoding context.
240  * @jpeg_enc:		JPEG-encoding context.
241  * @mpeg2_dec:		MPEG-2-decoding context.
242  * @vp8_dec:		VP8-decoding context.
243  * @hevc_dec:		HEVC-decoding context.
244  * @vp9_dec:		VP9-decoding context.
245  * @av1_dec:		AV1-decoding context.
280  * struct hantro_fmt - information about supported video formats.
289  * @postprocessed: Indicates if this format needs the post-processor.
352  * bit 0 - global information: mode, size, init, release
353  * bit 1 - each run start/result information
354  * bit 2 - contents of small controls from userspace
355  * bit 3 - contents of big controls from userspace
356  * bit 4 - detail fmt, ctrl, buffer q/dq information
357  * bit 5 - detail function enter/leave trace information
358  * bit 6 - register write/read information
383 	writel_relaxed(val, vpu->enc_base + reg);  in vepu_write_relaxed()
389 	writel(val, vpu->enc_base + reg);  in vepu_write()
394 	u32 val = readl(vpu->enc_base + reg);  in vepu_read()
404 	writel_relaxed(val, vpu->dec_base + reg);  in vdpu_write_relaxed()
410 	writel(val, vpu->dec_base + reg);  in vdpu_write()
422 	u32 val = readl(vpu->dec_base + reg);  in vdpu_read()
434 	v = vdpu_read(vpu, reg->base);  in vdpu_read_mask()
435 	v &= ~(reg->mask << reg->shift);  in vdpu_read_mask()
436 	v |= ((val & reg->mask) << reg->shift);  in vdpu_read_mask()
444 	vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);  in hantro_reg_write()
451 	vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);  in hantro_reg_write_relaxed()
460 	return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);  in hantro_get_src_buf()
466 	return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);  in hantro_get_dst_buf()
475 	if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))  in hantro_get_dec_buf_addr()
476 		return ctx->postproc.dec_q[vb->index].dma;  in hantro_get_dec_buf_addr()