20 void flite_hw_reset(struct fimc_lite *dev)  in flite_hw_reset()  argument
25 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
27 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
30 		cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
37 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
40 void flite_hw_clear_pending_irq(struct fimc_lite *dev)  in flite_hw_clear_pending_irq()  argument
42 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
44 	writel(cfg, dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
47 u32 flite_hw_get_interrupt_source(struct fimc_lite *dev)  in flite_hw_get_interrupt_source()  argument
49 	u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_get_interrupt_source()
53 void flite_hw_clear_last_capture_end(struct fimc_lite *dev)  in flite_hw_clear_last_capture_end()  argument
56 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
58 	writel(cfg, dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
61 void flite_hw_set_interrupt_mask(struct fimc_lite *dev)  in flite_hw_set_interrupt_mask()  argument
66 	if (atomic_read(&dev->out_path) == FIMC_IO_DMA) {  in flite_hw_set_interrupt_mask()
77 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
80 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
83 void flite_hw_capture_start(struct fimc_lite *dev)  in flite_hw_capture_start()  argument
85 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
87 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
90 void flite_hw_capture_stop(struct fimc_lite *dev)  in flite_hw_capture_stop()  argument
92 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
94 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
101 void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on)  in flite_hw_set_test_pattern()  argument
103 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
108 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
127 void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f)  in flite_hw_set_source_format()  argument
139 		v4l2_err(&dev->ve.vdev,  in flite_hw_set_source_format()
144 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
147 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
149 	cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
154 	writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
158 void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f)  in flite_hw_set_window_offset()  argument
163 	cfg = readl(dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
167 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
173 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);  in flite_hw_set_window_offset()
177 static void flite_hw_set_camera_port(struct fimc_lite *dev, int id)  in flite_hw_set_camera_port()  argument
179 	u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
184 	writel(cfg, dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
188 void flite_hw_set_camera_bus(struct fimc_lite *dev,  in flite_hw_set_camera_bus()  argument
191 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
212 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
214 	flite_hw_set_camera_port(dev, si->mux_id);  in flite_hw_set_camera_bus()
217 static void flite_hw_set_pack12(struct fimc_lite *dev, int on)  in flite_hw_set_pack12()  argument
219 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
226 	writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
229 static void flite_hw_set_out_order(struct fimc_lite *dev, struct flite_frame *f)  in flite_hw_set_out_order()  argument
237 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
244 	writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
247 void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f)  in flite_hw_set_dma_window()  argument
252 	cfg = readl(dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
255 	writel(cfg, dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
258 	cfg = readl(dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
261 	writel(cfg, dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
264 void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf)  in flite_hw_set_dma_buffer()  argument
269 	if (dev->dd->max_dma_bufs == 1)  in flite_hw_set_dma_buffer()
275 		writel(buf->addr, dev->regs + FLITE_REG_CIOSA);  in flite_hw_set_dma_buffer()
277 		writel(buf->addr, dev->regs + FLITE_REG_CIOSAN(index - 1));  in flite_hw_set_dma_buffer()
279 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
281 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
284 void flite_hw_mask_dma_buffer(struct fimc_lite *dev, u32 index)  in flite_hw_mask_dma_buffer()  argument
288 	if (dev->dd->max_dma_bufs == 1)  in flite_hw_mask_dma_buffer()
291 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
293 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
297 void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f,  in flite_hw_set_output_dma()  argument
300 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
304 		writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
309 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
311 	flite_hw_set_out_order(dev, f);  in flite_hw_set_output_dma()
312 	flite_hw_set_dma_window(dev, f);  in flite_hw_set_output_dma()
313 	flite_hw_set_pack12(dev, 0);  in flite_hw_set_output_dma()
316 void flite_hw_dump_regs(struct fimc_lite *dev, const char *label)  in flite_hw_dump_regs()  argument
339 	v4l2_info(&dev->subdev, "--- %s ---\n", label);  in flite_hw_dump_regs()
342 		u32 cfg = readl(dev->regs + registers[i].offset);  in flite_hw_dump_regs()
343 		v4l2_info(&dev->subdev, "%9s: 0x%08x\n",  in flite_hw_dump_regs()