Lines Matching +full:sama7g5 +full:- +full:isc
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries
9 * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS
11 * ISC video pipeline integrates the following submodules:
31 #include <linux/clk-provider.h>
43 #include <media/v4l2-ctrls.h>
44 #include <media/v4l2-device.h>
45 #include <media/v4l2-event.h>
46 #include <media/v4l2-image-sizes.h>
47 #include <media/v4l2-ioctl.h>
48 #include <media/v4l2-fwnode.h>
49 #include <media/v4l2-subdev.h>
50 #include <media/videobuf2-dma-contig.h>
52 #include "microchip-isc-regs.h"
53 #include "microchip-isc.h"
62 /* This is a list of the formats that the ISC can *output* */
129 /* This is a list of formats that the ISC can receive as *input* */
230 static void isc_sama7g5_config_csc(struct isc_device *isc) in isc_sama7g5_config_csc() argument
232 struct regmap *regmap = isc->regmap; in isc_sama7g5_config_csc()
235 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama7g5_config_csc()
237 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama7g5_config_csc()
239 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama7g5_config_csc()
241 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama7g5_config_csc()
243 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama7g5_config_csc()
245 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama7g5_config_csc()
249 static void isc_sama7g5_config_cbc(struct isc_device *isc) in isc_sama7g5_config_cbc() argument
251 struct regmap *regmap = isc->regmap; in isc_sama7g5_config_cbc()
254 regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness); in isc_sama7g5_config_cbc()
255 regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast); in isc_sama7g5_config_cbc()
261 static void isc_sama7g5_config_cc(struct isc_device *isc) in isc_sama7g5_config_cc() argument
263 struct regmap *regmap = isc->regmap; in isc_sama7g5_config_cc()
274 static void isc_sama7g5_config_ctrls(struct isc_device *isc, in isc_sama7g5_config_ctrls() argument
277 struct isc_ctrls *ctrls = &isc->ctrls; in isc_sama7g5_config_ctrls()
278 struct v4l2_ctrl_handler *hdl = &ctrls->handler; in isc_sama7g5_config_ctrls()
280 ctrls->contrast = 16; in isc_sama7g5_config_ctrls()
282 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16); in isc_sama7g5_config_ctrls()
285 static void isc_sama7g5_config_dpc(struct isc_device *isc) in isc_sama7g5_config_dpc() argument
287 u32 bay_cfg = isc->config.sd_format->cfa_baycfg; in isc_sama7g5_config_dpc()
288 struct regmap *regmap = isc->regmap; in isc_sama7g5_config_dpc()
296 static void isc_sama7g5_config_gam(struct isc_device *isc) in isc_sama7g5_config_gam() argument
298 struct regmap *regmap = isc->regmap; in isc_sama7g5_config_gam()
304 static void isc_sama7g5_config_rlp(struct isc_device *isc) in isc_sama7g5_config_rlp() argument
306 struct regmap *regmap = isc->regmap; in isc_sama7g5_config_rlp()
307 u32 rlp_mode = isc->config.rlp_cfg_mode; in isc_sama7g5_config_rlp()
309 regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, in isc_sama7g5_config_rlp()
314 static void isc_sama7g5_adapt_pipeline(struct isc_device *isc) in isc_sama7g5_adapt_pipeline() argument
316 isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE; in isc_sama7g5_adapt_pipeline()
321 /* index 0 --> gamma bipartite */
336 static int xisc_parse_dt(struct device *dev, struct isc_device *isc) in xisc_parse_dt() argument
338 struct device_node *np = dev->of_node; in xisc_parse_dt()
345 INIT_LIST_HEAD(&isc->subdev_entities); in xisc_parse_dt()
347 mipi_mode = of_property_read_bool(np, "microchip,mipi-mode"); in xisc_parse_dt()
359 ret = -EINVAL; in xisc_parse_dt()
367 ret = -ENOMEM; in xisc_parse_dt()
370 subdev_entity->epn = epn; in xisc_parse_dt()
375 subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW; in xisc_parse_dt()
378 subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW; in xisc_parse_dt()
381 subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW; in xisc_parse_dt()
384 subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | in xisc_parse_dt()
388 subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI; in xisc_parse_dt()
390 list_add_tail(&subdev_entity->list, &isc->subdev_entities); in xisc_parse_dt()
399 struct device *dev = &pdev->dev; in microchip_xisc_probe()
400 struct isc_device *isc; in microchip_xisc_probe() local
407 isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); in microchip_xisc_probe()
408 if (!isc) in microchip_xisc_probe()
409 return -ENOMEM; in microchip_xisc_probe()
411 platform_set_drvdata(pdev, isc); in microchip_xisc_probe()
412 isc->dev = dev; in microchip_xisc_probe()
418 isc->regmap = devm_regmap_init_mmio(dev, io_base, µchip_isc_regmap_config); in microchip_xisc_probe()
419 if (IS_ERR(isc->regmap)) { in microchip_xisc_probe()
420 ret = PTR_ERR(isc->regmap); in microchip_xisc_probe()
430 "microchip-sama7g5-xisc", isc); in microchip_xisc_probe()
437 isc->gamma_table = isc_sama7g5_gamma_table; in microchip_xisc_probe()
438 isc->gamma_max = 0; in microchip_xisc_probe()
440 isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH; in microchip_xisc_probe()
441 isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; in microchip_xisc_probe()
443 isc->config_dpc = isc_sama7g5_config_dpc; in microchip_xisc_probe()
444 isc->config_csc = isc_sama7g5_config_csc; in microchip_xisc_probe()
445 isc->config_cbc = isc_sama7g5_config_cbc; in microchip_xisc_probe()
446 isc->config_cc = isc_sama7g5_config_cc; in microchip_xisc_probe()
447 isc->config_gam = isc_sama7g5_config_gam; in microchip_xisc_probe()
448 isc->config_rlp = isc_sama7g5_config_rlp; in microchip_xisc_probe()
449 isc->config_ctrls = isc_sama7g5_config_ctrls; in microchip_xisc_probe()
451 isc->adapt_pipeline = isc_sama7g5_adapt_pipeline; in microchip_xisc_probe()
453 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; in microchip_xisc_probe()
454 isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET; in microchip_xisc_probe()
455 isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET; in microchip_xisc_probe()
456 isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET; in microchip_xisc_probe()
457 isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET; in microchip_xisc_probe()
458 isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET; in microchip_xisc_probe()
459 isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET; in microchip_xisc_probe()
460 isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET; in microchip_xisc_probe()
461 isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET; in microchip_xisc_probe()
463 isc->controller_formats = sama7g5_controller_formats; in microchip_xisc_probe()
464 isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats); in microchip_xisc_probe()
465 isc->formats_list = sama7g5_formats_list; in microchip_xisc_probe()
466 isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list); in microchip_xisc_probe()
468 /* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */ in microchip_xisc_probe()
469 isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32; in microchip_xisc_probe()
471 /* sama7g5-isc : ISPCK does not exist, ISC is clocked by MCK */ in microchip_xisc_probe()
472 isc->ispck_required = false; in microchip_xisc_probe()
474 ret = microchip_isc_pipeline_init(isc); in microchip_xisc_probe()
478 isc->hclock = devm_clk_get(dev, "hclock"); in microchip_xisc_probe()
479 if (IS_ERR(isc->hclock)) { in microchip_xisc_probe()
480 ret = PTR_ERR(isc->hclock); in microchip_xisc_probe()
485 ret = clk_prepare_enable(isc->hclock); in microchip_xisc_probe()
491 ret = microchip_isc_clk_init(isc); in microchip_xisc_probe()
493 dev_err(dev, "failed to init isc clock: %d\n", ret); in microchip_xisc_probe()
497 ret = v4l2_device_register(dev, &isc->v4l2_dev); in microchip_xisc_probe()
503 ret = xisc_parse_dt(dev, isc); in microchip_xisc_probe()
509 if (list_empty(&isc->subdev_entities)) { in microchip_xisc_probe()
511 ret = -ENODEV; in microchip_xisc_probe()
515 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { in microchip_xisc_probe()
518 of_fwnode_handle(subdev_entity->epn); in microchip_xisc_probe()
520 v4l2_async_nf_init(&subdev_entity->notifier, &isc->v4l2_dev); in microchip_xisc_probe()
522 asd = v4l2_async_nf_add_fwnode_remote(&subdev_entity->notifier, in microchip_xisc_probe()
526 of_node_put(subdev_entity->epn); in microchip_xisc_probe()
527 subdev_entity->epn = NULL; in microchip_xisc_probe()
534 subdev_entity->notifier.ops = µchip_isc_async_ops; in microchip_xisc_probe()
536 ret = v4l2_async_nf_register(&subdev_entity->notifier); in microchip_xisc_probe()
542 if (video_is_registered(&isc->video_dev)) in microchip_xisc_probe()
546 regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); in microchip_xisc_probe()
548 ret = isc_mc_init(isc, ver); in microchip_xisc_probe()
561 isc_mc_cleanup(isc); in microchip_xisc_probe()
564 microchip_isc_subdev_cleanup(isc); in microchip_xisc_probe()
567 v4l2_device_unregister(&isc->v4l2_dev); in microchip_xisc_probe()
570 clk_disable_unprepare(isc->hclock); in microchip_xisc_probe()
572 microchip_isc_clk_cleanup(isc); in microchip_xisc_probe()
579 struct isc_device *isc = platform_get_drvdata(pdev); in microchip_xisc_remove() local
581 pm_runtime_disable(&pdev->dev); in microchip_xisc_remove()
583 isc_mc_cleanup(isc); in microchip_xisc_remove()
585 microchip_isc_subdev_cleanup(isc); in microchip_xisc_remove()
587 v4l2_device_unregister(&isc->v4l2_dev); in microchip_xisc_remove()
589 clk_disable_unprepare(isc->hclock); in microchip_xisc_remove()
591 microchip_isc_clk_cleanup(isc); in microchip_xisc_remove()
596 struct isc_device *isc = dev_get_drvdata(dev); in xisc_runtime_suspend() local
598 clk_disable_unprepare(isc->hclock); in xisc_runtime_suspend()
605 struct isc_device *isc = dev_get_drvdata(dev); in xisc_runtime_resume() local
608 ret = clk_prepare_enable(isc->hclock); in xisc_runtime_resume()
621 { .compatible = "microchip,sama7g5-isc" },
631 .name = "microchip-sama7g5-xisc",
640 MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC");