Lines Matching +full:20 +full:product

114 #define ISC_DPC_CFG_GDCCLP_SHIFT	20
115 #define ISC_DPC_CFG_GDCCLP_MASK		GENMASK(22, 20)
226 /* Offset for CSC register specific to sama5d2 product */
228 /* Offset for CSC register specific to sama7g5 product */
252 /* Offset for CBC register specific to sama5d2 product */
254 /* Offset for CBC register specific to sama7g5 product */
276 /* Offset for SUB422 register specific to sama5d2 product */
278 /* Offset for SUB422 register specific to sama7g5 product */
284 /* Offset for SUB420 register specific to sama5d2 product */
286 /* Offset for SUB420 register specific to sama7g5 product */
291 /* Offset for RLP register specific to sama5d2 product */
293 /* Offset for RLP register specific to sama7g5 product */
323 /* Offset for HIS register specific to sama5d2 product */
325 /* Offset for HIS register specific to sama7g5 product */
348 /* Offset for DMA register specific to sama5d2 product */
350 /* Offset for DMA register specific to sama7g5 product */
400 /* Offset for version register specific to sama5d2 product */
406 /* Offset for version register specific to sama5d2 product */
408 /* Offset for version register specific to sama7g5 product */