Lines Matching defs:vpu_enc_config_params
178 struct vpu_enc_config_params { struct
179 u32 param_change;
180 u32 start_frame;
181 u32 end_frame;
182 u32 userdata_enable;
183 u32 userdata_id[4];
184 u32 userdata_message[WINDSOR_USER_DATA_WORDS];
185 u32 userdata_length;
186 u32 h264_profile_idc;
187 u32 h264_level_idc;
188 u32 h264_au_delimiter;
189 u32 h264_seq_end_code;
190 u32 h264_recovery_points;
191 u32 h264_vui_parameters;
192 u32 h264_aspect_ratio_present;
193 u32 h264_aspect_ratio_sar_width;
194 u32 h264_aspect_ratio_sar_height;
195 u32 h264_overscan_present;
196 u32 h264_video_type_present;
197 u32 h264_video_format;
198 u32 h264_video_full_range;
199 u32 h264_video_colour_descriptor;
200 u32 h264_video_colour_primaries;
201 u32 h264_video_transfer_char;
202 u32 h264_video_matrix_coeff;
203 u32 h264_chroma_loc_info_present;
204 u32 h264_chroma_loc_type_top;
205 u32 h264_chroma_loc_type_bot;
206 u32 h264_timing_info_present;
207 u32 h264_buffering_period_present;
208 u32 h264_low_delay_hrd_flag;
209 u32 aspect_ratio;
210 u32 test_mode; // Automated firmware test mode
211 u32 dsa_test_mode; // Automated test mode for the DSA.
212 u32 fme_test_mode; // Automated test mode for the fme
213 u32 cbr_row_mode; //0: FW mode; 1: HW mode
214 u32 windsor_mode; //0: normal mode; 1: intra only mode; 2: intra+0MV mode
215 u32 encode_mode; // H264, VC1, MPEG2, DIVX
216 u32 frame_width; // display width
217 u32 frame_height; // display height
218 u32 enc_frame_width; // encoding width, should be 16-pix align
219 u32 enc_frame_height; // encoding height, should be 16-pix aligned
220 u32 frame_rate_num;
221 u32 frame_rate_den;
222 u32 vi_field_source;
223 u32 vi_frame_width;
224 u32 vi_frame_height;
225 u32 crop_frame_width;
226 u32 crop_frame_height;
227 u32 crop_x_start_posn;
228 u32 crop_y_start_posn;
229 u32 mode422;
230 u32 mode_yuy2;
231 u32 dsa_luma_en;
232 u32 dsa_chroma_en;
233 u32 dsa_ext_hfilt_en;
234 u32 dsa_di_en;
235 u32 dsa_di_top_ref;
236 u32 dsa_vertf_disable;
237 u32 dsa_disable_pwb;
238 u32 dsa_hor_phase;
239 u32 dsa_ver_phase;
240 u32 dsa_iac_enable;
241 u32 iac_sc_threshold;
242 u32 iac_vm_threshold;
243 u32 iac_skip_mode;
244 u32 iac_grp_width;
245 u32 iac_grp_height;
246 u32 rate_control_mode;
247 u32 rate_control_resolution;
248 u32 buffer_size;
249 u32 buffer_level_init;
250 u32 buffer_I_bit_budget;
251 u32 top_field_first;
252 u32 intra_lum_qoffset;
253 u32 intra_chr_qoffset;
254 u32 inter_lum_qoffset;
255 u32 inter_chr_qoffset;
256 u32 use_def_scaling_mtx;
257 u32 inter_8x8_enab;
258 u32 inter_4x4_enab;
259 u32 fme_enable_qpel;
260 u32 fme_enable_hpel;
261 u32 fme_nozeromv;
262 u32 fme_predmv_en;
263 u32 fme_pred_2mv4mv;
264 u32 fme_smallsadthresh;
265 u32 ame_en_lmvc;
266 u32 ame_x_mult;
267 u32 cme_enable_4mv;
268 u32 cme_enable_1mv;
269 u32 hme_enable_16x8mv;
270 u32 hme_enable_8x16mv;
271 u32 cme_mv_weight;
272 u32 cme_mv_cost;
273 u32 ame_mult_mv;
274 u32 ame_shift_mv;
275 u32 hme_forceto1mv_en;
276 u32 hme_2mv_cost;
277 u32 hme_pred_mode;
278 u32 hme_sc_rnge;
279 u32 hme_sw_rnge;
280 u32 output_format;
281 u32 timestamp_enab;
282 u32 initial_pts_enab;
283 u32 initial_pts;