113 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_pinnacle_init()
115 	mt352_write(fe, reset,          sizeof(reset));  in mt352_pinnacle_init()
116 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_pinnacle_init()
117 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_pinnacle_init()
118 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_pinnacle_init()
119 	mt352_write(fe, gpp_ctl_cfg,    sizeof(gpp_ctl_cfg));  in mt352_pinnacle_init()
121 	mt352_write(fe, fsm_ctl_cfg,    sizeof(fsm_ctl_cfg));  in mt352_pinnacle_init()
122 	mt352_write(fe, scan_ctl_cfg,   sizeof(scan_ctl_cfg));  in mt352_pinnacle_init()
123 	mt352_write(fe, irq_cfg,        sizeof(irq_cfg));  in mt352_pinnacle_init()
136 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_aver777_init()
138 	mt352_write(fe, reset,          sizeof(reset));  in mt352_aver777_init()
139 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_aver777_init()
140 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_aver777_init()
141 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_aver777_init()
154 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_avermedia_xc3028_init()
156 	mt352_write(fe, reset,          sizeof(reset));  in mt352_avermedia_xc3028_init()
157 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_avermedia_xc3028_init()
158 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_avermedia_xc3028_init()
159 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_avermedia_xc3028_init()