361 #define dm_writeb(reg, value)	outb((value), (dm_io_mem(reg)))  macro
483 		dm_writeb(DM1105_I2CCTR, 0x00);  in dm1105_i2c_xfer()
488 			dm_writeb(DM1105_I2CDAT, addr);  in dm1105_i2c_xfer()
490 				dm_writeb(DM1105_I2CDAT + byte + 1, 0);  in dm1105_i2c_xfer()
492 			dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);  in dm1105_i2c_xfer()
514 				dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);  in dm1105_i2c_xfer()
515 				dm_writeb(DM1105_I2CDAT + 1, 0xf7);  in dm1105_i2c_xfer()
518 					dm_writeb(DM1105_I2CDAT + byte + 2, data);  in dm1105_i2c_xfer()
520 				dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));  in dm1105_i2c_xfer()
536 			dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);  in dm1105_i2c_xfer()
539 				dm_writeb(DM1105_I2CDAT + byte + 1, data);  in dm1105_i2c_xfer()
541 			dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);  in dm1105_i2c_xfer()
622 	dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK);  in dm1105_enable_irqs()
623 	dm_writeb(DM1105_CR, 1);  in dm1105_enable_irqs()
628 	dm_writeb(DM1105_INTMAK, INTMAK_IRM);  in dm1105_disable_irqs()
629 	dm_writeb(DM1105_CR, 0);  in dm1105_disable_irqs()
683 			dm_writeb(DM1105_RST, 1);  in dm1105_dmx_buffer()
707 	dm_writeb(DM1105_INTSTS, intsts);  in dm1105_irq()
772 	dm_writeb(DM1105_HOST_CTR, 0);  in dm1105_hw_init()
775 	dm_writeb(DM1105_DTALENTH, 188);  in dm1105_hw_init()
784 	dm_writeb(DM1105_INTCNT, 47);  in dm1105_hw_init()
787 	dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK));  in dm1105_hw_init()
788 	dm_writeb(DM1105_IRMODE, 0);  in dm1105_hw_init()
799 	dm_writeb(DM1105_IRCTR, 0);  in dm1105_hw_exit()
800 	dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK);  in dm1105_hw_exit()