Lines Matching +full:src +full:- +full:ref +full:- +full:clk +full:- +full:mhz
1 // SPDX-License-Identifier: GPL-2.0-only
3 * TC358746 - Parallel <-> CSI-2 Bridge
8 * - Currently only 'Parallel-in -> CSI-out' mode is supported!
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-mc.h>
29 /* 16-bit registers */
80 /* 32-bit registers */
150 struct clk *refclk;
236 /* Get n-th format for pad */
246 if ((pad == TC358746_SOURCE && fmt->csi_format) || in tc358746_get_format_by_idx()
254 return ERR_PTR(-EINVAL); in tc358746_get_format_by_idx()
265 if (pad == TC358746_SINK && fmt->code == code) in tc358746_get_format_by_code()
268 if (pad == TC358746_SOURCE && !fmt->csi_format) in tc358746_get_format_by_code()
271 if (fmt->code == code) in tc358746_get_format_by_code()
275 return ERR_PTR(-EINVAL); in tc358746_get_format_by_code()
316 /* 32-bit registers starting from CLW_DPHYCONTTX */ in tc358746_write()
319 err = regmap_bulk_write(tc358746->regmap, reg, &val, count); in tc358746_write()
321 dev_err(tc358746->sd.dev, in tc358746_write()
332 /* 32-bit registers starting from CLW_DPHYCONTTX */ in tc358746_read()
336 err = regmap_bulk_read(tc358746->regmap, reg, val, count); in tc358746_read()
338 dev_err(tc358746->sd.dev, in tc358746_read()
386 u8 post = tc358746->pll_post_div; in tc358746_apply_pll_config()
387 u16 pre = tc358746->pll_pre_div; in tc358746_apply_pll_config()
388 u16 mul = tc358746->pll_mul; in tc358746_apply_pll_config()
400 /* Pre-div and Multiplicator have a internal +1 logic */ in tc358746_apply_pll_config()
401 val = PLL_PRD(pre - 1) | PLL_FBD(mul - 1); in tc358746_apply_pll_config()
421 struct v4l2_subdev *sd = &tc358746->sd; in tc358746_apply_misc_config()
424 struct device *dev = sd->dev; in tc358746_apply_misc_config()
431 fmt = tc358746_get_format_by_code(TC358746_SINK, mbusfmt->code); in tc358746_apply_misc_config()
434 val = PDFMT(fmt->pdformat); in tc358746_apply_misc_config()
440 val = PDATAF(fmt->pdataf); in tc358746_apply_misc_config()
441 dev_dbg(dev, "CONFCTL[PDATAF]: 0x%x\n", fmt->pdataf); in tc358746_apply_misc_config()
446 val = tc358746->vb_size / 32; in tc358746_apply_misc_config()
453 val = mbusfmt->width * fmt->bpp / 8; in tc358746_apply_misc_config()
463 /* Use MHz as base so the div needs no u64 */
485 struct phy_configure_opts_mipi_dphy *cfg = &tc358746->dphy_cfg; in tc358746_apply_dphy_config()
486 bool non_cont_clk = !!(tc358746->csi_vep.bus.mipi_csi2.flags & in tc358746_apply_dphy_config()
488 struct device *dev = tc358746->sd.dev; in tc358746_apply_dphy_config()
494 hs_byte_clk = cfg->hs_clk_rate / 8; in tc358746_apply_dphy_config()
498 val = tc358746_us_to_cnt(cfg->init, hf_clk) - 1; in tc358746_apply_dphy_config()
504 val = tc358746_ps_to_cnt(cfg->lpx, hs_byte_clk) - 1; in tc358746_apply_dphy_config()
511 val = tc358746_ps_to_cnt(cfg->clk_prepare, hs_byte_clk) - 1; in tc358746_apply_dphy_config()
512 val2 = tc358746_ps_to_cnt(cfg->clk_zero, hs_byte_clk) - 1; in tc358746_apply_dphy_config()
522 val = tc358746_ps_to_cnt(cfg->clk_trail, hs_byte_clk); in tc358746_apply_dphy_config()
528 val = tc358746_ps_to_cnt(cfg->hs_prepare, hs_byte_clk) - 1; in tc358746_apply_dphy_config()
529 val2 = tc358746_ps_to_cnt(cfg->hs_zero, hs_byte_clk) - 1; in tc358746_apply_dphy_config()
540 val = tc358746_us_to_cnt(cfg->wakeup, hs_byte_clk); in tc358746_apply_dphy_config()
541 val = val / (lptxcnt + 1) - 1; in tc358746_apply_dphy_config()
547 val = tc358746_ps_to_cnt(cfg->clk_post, hs_byte_clk); in tc358746_apply_dphy_config()
553 val = tc358746_ps_to_cnt(cfg->hs_trail, hs_byte_clk); in tc358746_apply_dphy_config()
568 unsigned int lanes = tc358746->dphy_cfg.lanes; in tc358746_enable_csi_lanes()
574 lanes - 1); in tc358746_enable_csi_lanes()
580 dev_dbg(tc358746->sd.dev, "CLW_CNTRL: 0x%x\n", val); in tc358746_enable_csi_lanes()
590 dev_dbg(tc358746->sd.dev, "D%uW_CNTRL: 0x%x\n", lane, val); in tc358746_enable_csi_lanes()
606 dev_dbg(tc358746->sd.dev, "HSTXVREGEN: 0x%x\n", val); in tc358746_enable_csi_lanes()
613 unsigned int lanes = tc358746->dphy_cfg.lanes; in tc358746_enable_csi_module()
618 * required to put the lane state back into LP-11 state. The sw reset in tc358746_enable_csi_module()
636 DATA(CSI_MODE | TXHSMD | NOL(lanes - 1))); in tc358746_enable_csi_module()
668 return media_entity_to_v4l2_subdev(pad->entity); in tc358746_get_remote_sd()
674 struct v4l2_subdev *src; in tc358746_s_stream() local
677 dev_dbg(sd->dev, "%sable\n", enable ? "en" : "dis"); in tc358746_s_stream()
679 src = tc358746_get_remote_sd(&tc358746->pads[TC358746_SINK]); in tc358746_s_stream()
680 if (!src) in tc358746_s_stream()
681 return -EPIPE; in tc358746_s_stream()
684 err = pm_runtime_resume_and_get(sd->dev); in tc358746_s_stream()
708 err = v4l2_subdev_call(src, video, s_stream, 1); in tc358746_s_stream()
715 pm_runtime_mark_last_busy(sd->dev); in tc358746_s_stream()
716 pm_runtime_put_sync_autosuspend(sd->dev); in tc358746_s_stream()
723 * LP-11 state is entered correctly. in tc358746_s_stream()
737 pm_runtime_mark_last_busy(sd->dev); in tc358746_s_stream()
738 pm_runtime_put_sync_autosuspend(sd->dev); in tc358746_s_stream()
740 return v4l2_subdev_call(src, video, s_stream, 0); in tc358746_s_stream()
753 fmt->code = tc358746_src_mbus_code(tc358746_def_fmt.code); in tc358746_init_cfg()
764 fmt = tc358746_get_format_by_idx(code->pad, code->index); in tc358746_enum_mbus_code()
768 code->code = fmt->code; in tc358746_enum_mbus_code()
781 if (format->pad == TC358746_SOURCE) in tc358746_set_fmt()
786 fmt = tc358746_get_format_by_code(format->pad, format->format.code); in tc358746_set_fmt()
788 fmt = tc358746_get_format_by_code(format->pad, tc358746_def_fmt.code); in tc358746_set_fmt()
790 format->format.code = fmt->code; in tc358746_set_fmt()
791 format->format.field = V4L2_FIELD_NONE; in tc358746_set_fmt()
793 dev_dbg(sd->dev, "Update format: %ux%u code:0x%x -> %ux%u code:0x%x", in tc358746_set_fmt()
794 sink_fmt->width, sink_fmt->height, sink_fmt->code, in tc358746_set_fmt()
795 format->format.width, format->format.height, format->format.code); in tc358746_set_fmt()
797 *sink_fmt = format->format; in tc358746_set_fmt()
801 src_fmt->code = tc358746_src_mbus_code(sink_fmt->code); in tc358746_set_fmt()
811 struct device *dev = tc358746->sd.dev; in tc358746_find_pll_settings()
821 dev_err(dev, "HS-Clock above 1 Ghz are not supported\n"); in tc358746_find_pll_settings()
851 delta = abs(fout - tmp); in tc358746_find_pll_settings()
868 tc358746->pll_post_div = postdiv; in tc358746_find_pll_settings()
869 tc358746->pll_pre_div = p_best; in tc358746_find_pll_settings()
870 tc358746->pll_mul = m_best; in tc358746_find_pll_settings()
907 fmt = tc358746_get_format_by_code(TC358746_SINK, mbusfmt->code); in tc358746_link_validate()
909 source = media_entity_to_v4l2_subdev(link->source->entity); in tc358746_link_validate()
910 source_link_freq = v4l2_get_link_freq(source->ctrl_handler, 0, 0); in tc358746_link_validate()
912 dev_err(tc358746->sd.dev, in tc358746_link_validate()
915 /* Return -EINVAL in case of source_link_freq is 0 */ in tc358746_link_validate()
916 return source_link_freq ? : -EINVAL; in tc358746_link_validate()
918 source_bitrate = source_link_freq * fmt->bus_width; in tc358746_link_validate()
920 csi_bitrate = tc358746->dphy_cfg.lanes * tc358746->pll_rate; in tc358746_link_validate()
922 dev_dbg(tc358746->sd.dev, in tc358746_link_validate()
923 "Fifo settings params: source-bitrate:%lu csi-bitrate:%lu", in tc358746_link_validate()
929 return -EINVAL; in tc358746_link_validate()
935 tc358746->vb_size = TC358746_VB_DEFAULT_SIZE; in tc358746_link_validate()
946 * fifo-sz, image-width - in bits in tc358746_link_validate()
947 * sbr - source_bitrate in bits/s in tc358746_link_validate()
948 * csir - csi_bitrate in bits/s in tc358746_link_validate()
950 * image-width / csir >= (image-width - fifo-sz) / sbr in tc358746_link_validate()
951 * image-width * sbr / csir >= image-width - fifo-sz in tc358746_link_validate()
952 * fifo-sz >= image-width - image-width * sbr / csir; with n = csir/sbr in tc358746_link_validate()
953 * fifo-sz >= image-width - image-width / n in tc358746_link_validate()
958 tmp = (mbusfmt->width * TC358746_PRECISION) / n; in tc358746_link_validate()
959 fifo_sz = mbusfmt->width - tmp; in tc358746_link_validate()
960 fifo_sz *= fmt->bpp; in tc358746_link_validate()
961 tc358746->vb_size = round_up(fifo_sz, 32); in tc358746_link_validate()
964 dev_dbg(tc358746->sd.dev, in tc358746_link_validate()
965 "Found FIFO size[bits]:%u -> aligned to size[bits]:%u\n", in tc358746_link_validate()
966 fifo_sz, tc358746->vb_size); in tc358746_link_validate()
970 return tc358746->vb_size > TC358746_VB_MAX_SIZE ? -EINVAL : 0; in tc358746_link_validate()
979 return -EINVAL; in tc358746_get_mbus_config()
981 config->type = V4L2_MBUS_CSI2_DPHY; in tc358746_get_mbus_config()
982 config->bus.mipi_csi2 = tc358746->csi_vep.bus.mipi_csi2; in tc358746_get_mbus_config()
994 /* 32-bit registers starting from CLW_DPHYCONTTX */ in tc358746_g_register()
995 reg->size = reg->reg < CLW_DPHYCONTTX_REG ? 2 : 4; in tc358746_g_register()
997 if (!pm_runtime_get_if_in_use(sd->dev)) in tc358746_g_register()
1000 err = tc358746_read(tc358746, reg->reg, &val); in tc358746_g_register()
1001 reg->val = val; in tc358746_g_register()
1003 pm_runtime_mark_last_busy(sd->dev); in tc358746_g_register()
1004 pm_runtime_put_sync_autosuspend(sd->dev); in tc358746_g_register()
1014 if (!pm_runtime_get_if_in_use(sd->dev)) in tc358746_s_register()
1017 tc358746_write(tc358746, (u32)reg->reg, (u32)reg->val); in tc358746_s_register()
1019 pm_runtime_mark_last_busy(sd->dev); in tc358746_s_register()
1020 pm_runtime_put_sync_autosuspend(sd->dev); in tc358746_s_register()
1063 div = tc358746->mclk_postdiv / 2; in tc358746_mclk_enable()
1064 val = MCLK_HIGH(div - 1) | MCLK_LOW(div - 1); in tc358746_mclk_enable()
1065 dev_dbg(tc358746->sd.dev, "MCLKCTL: %u (0x%x)\n", val, val); in tc358746_mclk_enable()
1070 if (tc358746->mclk_prediv == 8) in tc358746_mclk_enable()
1072 else if (tc358746->mclk_prediv == 4) in tc358746_mclk_enable()
1077 dev_dbg(tc358746->sd.dev, "CLKCTL[MCLKDIV]: %u (0x%x)\n", val, val); in tc358746_mclk_enable()
1092 unsigned long pll_rate = tc358746->pll_rate; in tc358746_find_mclk_settings()
1095 struct device *dev = tc358746->sd.dev; in tc358746_find_mclk_settings()
1101 * MCLK-Div in tc358746_find_mclk_settings()
1102 * -------------------´`--------------------- in tc358746_find_mclk_settings()
1104 * +-------------+ +------------------------+ in tc358746_find_mclk_settings()
1105 * | MCLK-PreDiv | | MCLK-PostDiv | in tc358746_find_mclk_settings()
1106 * PLL --> | (2/4/8) | --> | (mclk_low + mclk_high) | --> MCLK in tc358746_find_mclk_settings()
1107 * +-------------+ +------------------------+ in tc358746_find_mclk_settings()
1110 * mclk_low/high = 1 --> 2 MCLK-Ref Counts in tc358746_find_mclk_settings()
1111 * mclk_low/high = 255 --> 256 MCLK-Ref Counts == max. in tc358746_find_mclk_settings()
1117 * MCLK = PLL / (MCLK-PreDiv * 2 * MCLK-PostDiv) in tc358746_find_mclk_settings()
1120 if (mclk_rate == tc358746->mclk_rate) in tc358746_find_mclk_settings()
1160 /* The MCLK <-> PLL gap is to high -> use largest possible div */ in tc358746_find_mclk_settings()
1166 tc358746->mclk_prediv = mclk_prediv; in tc358746_find_mclk_settings()
1167 tc358746->mclk_postdiv = mclk_postdiv; in tc358746_find_mclk_settings()
1168 tc358746->mclk_rate = best_mclk_rate; in tc358746_find_mclk_settings()
1207 return tc358746->pll_rate / (prediv * postdiv); in tc358746_recalc_rate()
1215 *parent_rate = tc358746->pll_rate; in tc358746_mclk_round_rate()
1241 struct device *dev = tc358746->sd.dev; in tc358746_setup_mclk_provider()
1245 /* MCLK clk provider support is optional */ in tc358746_setup_mclk_provider()
1246 if (!device_property_present(dev, "#clock-cells")) in tc358746_setup_mclk_provider()
1250 tc358746->mclk_postdiv = 512; in tc358746_setup_mclk_provider()
1251 tc358746->mclk_prediv = 8; in tc358746_setup_mclk_provider()
1253 mclk_name = "tc358746-mclk"; in tc358746_setup_mclk_provider()
1254 device_property_read_string(dev, "clock-output-names", &mclk_name); in tc358746_setup_mclk_provider()
1258 tc358746->mclk_hw.init = &mclk_initdata; in tc358746_setup_mclk_provider()
1260 err = devm_clk_hw_register(dev, &tc358746->mclk_hw); in tc358746_setup_mclk_provider()
1267 &tc358746->mclk_hw); in tc358746_setup_mclk_provider()
1277 struct v4l2_subdev *sd = &tc358746->sd; in tc358746_init_subdev()
1281 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; in tc358746_init_subdev()
1282 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; in tc358746_init_subdev()
1283 sd->entity.ops = &tc358746_entity_ops; in tc358746_init_subdev()
1285 tc358746->pads[TC358746_SINK].flags = MEDIA_PAD_FL_SINK; in tc358746_init_subdev()
1286 tc358746->pads[TC358746_SOURCE].flags = MEDIA_PAD_FL_SOURCE; in tc358746_init_subdev()
1287 err = media_entity_pads_init(&sd->entity, TC358746_NR_PADS, in tc358746_init_subdev()
1288 tc358746->pads); in tc358746_init_subdev()
1294 media_entity_cleanup(&sd->entity); in tc358746_init_subdev()
1302 struct device *dev = tc358746->sd.dev; in tc358746_init_output_port()
1313 return -EINVAL; in tc358746_init_output_port()
1316 /* Currently we only support 'parallel in' -> 'csi out' */ in tc358746_init_output_port()
1317 vep = &tc358746->csi_vep; in tc358746_init_output_port()
1318 vep->bus_type = V4L2_MBUS_CSI2_DPHY; in tc358746_init_output_port()
1326 csi_lanes = vep->bus.mipi_csi2.num_data_lanes; in tc358746_init_output_port()
1328 vep->nr_of_link_frequencies == 0) { in tc358746_init_output_port()
1329 dev_err(dev, "error: Invalid CSI-2 settings\n"); in tc358746_init_output_port()
1330 err = -EINVAL; in tc358746_init_output_port()
1335 csi_link_rate = (unsigned long)vep->link_frequencies[0]; in tc358746_init_output_port()
1336 tc358746->pll_rate = tc358746_find_pll_settings(tc358746, refclk, in tc358746_init_output_port()
1338 if (!tc358746->pll_rate) { in tc358746_init_output_port()
1339 err = -EINVAL; in tc358746_init_output_port()
1343 err = phy_mipi_dphy_get_default_config_for_hsclk(tc358746->pll_rate, in tc358746_init_output_port()
1344 csi_lanes, &tc358746->dphy_cfg); in tc358746_init_output_port()
1348 tc358746->vb_size = TC358746_VB_DEFAULT_SIZE; in tc358746_init_output_port()
1360 struct device *dev = tc358746->sd.dev; in tc358746_init_hw()
1371 /* Ensure that CSI interface is put into LP-11 state */ in tc358746_init_hw()
1383 return -ENODEV; in tc358746_init_hw()
1388 return -ENODEV; in tc358746_init_hw()
1396 u64 *link_frequencies = tc358746->csi_vep.link_frequencies; in tc358746_init_controls()
1400 err = v4l2_ctrl_handler_init(&tc358746->ctrl_hdl, 1); in tc358746_init_controls()
1405 * The driver currently supports only one link-frequency, regardless of in tc358746_init_controls()
1410 ctrl = v4l2_ctrl_new_int_menu(&tc358746->ctrl_hdl, NULL, in tc358746_init_controls()
1414 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; in tc358746_init_controls()
1416 err = tc358746->ctrl_hdl.error; in tc358746_init_controls()
1418 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl); in tc358746_init_controls()
1422 tc358746->sd.ctrl_handler = &tc358746->ctrl_hdl; in tc358746_init_controls()
1434 struct media_pad *sink = &tc358746->pads[TC358746_SINK]; in tc358746_notify_bound()
1452 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(tc358746->sd.dev), in tc358746_async_register()
1455 return -ENOTCONN; in tc358746_async_register()
1463 v4l2_async_subdev_nf_init(&tc358746->notifier, &tc358746->sd); in tc358746_async_register()
1464 asd = v4l2_async_nf_add_fwnode_remote(&tc358746->notifier, ep, in tc358746_async_register()
1473 tc358746->notifier.ops = &tc358746_notify_ops; in tc358746_async_register()
1475 err = v4l2_async_nf_register(&tc358746->notifier); in tc358746_async_register()
1479 err = v4l2_async_register_subdev(&tc358746->sd); in tc358746_async_register()
1486 v4l2_async_nf_unregister(&tc358746->notifier); in tc358746_async_register()
1488 v4l2_async_nf_cleanup(&tc358746->notifier); in tc358746_async_register()
1495 struct device *dev = &client->dev; in tc358746_probe()
1501 tc358746 = devm_kzalloc(&client->dev, sizeof(*tc358746), GFP_KERNEL); in tc358746_probe()
1503 return -ENOMEM; in tc358746_probe()
1505 tc358746->regmap = devm_regmap_init_i2c(client, &tc358746_regmap_config); in tc358746_probe()
1506 if (IS_ERR(tc358746->regmap)) in tc358746_probe()
1507 return dev_err_probe(dev, PTR_ERR(tc358746->regmap), in tc358746_probe()
1510 tc358746->refclk = devm_clk_get(dev, "refclk"); in tc358746_probe()
1511 if (IS_ERR(tc358746->refclk)) in tc358746_probe()
1512 return dev_err_probe(dev, PTR_ERR(tc358746->refclk), in tc358746_probe()
1515 err = clk_prepare_enable(tc358746->refclk); in tc358746_probe()
1520 refclk = clk_get_rate(tc358746->refclk); in tc358746_probe()
1521 clk_disable_unprepare(tc358746->refclk); in tc358746_probe()
1524 return dev_err_probe(dev, -EINVAL, "Invalid refclk range\n"); in tc358746_probe()
1527 tc358746->supplies[i].supply = tc358746_supplies[i]; in tc358746_probe()
1530 tc358746->supplies); in tc358746_probe()
1534 tc358746->reset_gpio = devm_gpiod_get_optional(dev, "reset", in tc358746_probe()
1536 if (IS_ERR(tc358746->reset_gpio)) in tc358746_probe()
1537 return dev_err_probe(dev, PTR_ERR(tc358746->reset_gpio), in tc358746_probe()
1538 "Failed to get reset-gpios\n"); in tc358746_probe()
1549 * Keep this order since we need the output port link-frequencies in tc358746_probe()
1575 dev_dbg(dev, "%s found @ 0x%x (%s)\n", client->name, in tc358746_probe()
1576 client->addr, client->adapter->name); in tc358746_probe()
1584 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl); in tc358746_probe()
1586 v4l2_fwnode_endpoint_free(&tc358746->csi_vep); in tc358746_probe()
1588 v4l2_subdev_cleanup(&tc358746->sd); in tc358746_probe()
1589 media_entity_cleanup(&tc358746->sd.entity); in tc358746_probe()
1600 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl); in tc358746_remove()
1601 v4l2_fwnode_endpoint_free(&tc358746->csi_vep); in tc358746_remove()
1602 v4l2_async_nf_unregister(&tc358746->notifier); in tc358746_remove()
1603 v4l2_async_nf_cleanup(&tc358746->notifier); in tc358746_remove()
1605 media_entity_cleanup(&sd->entity); in tc358746_remove()
1607 pm_runtime_disable(sd->dev); in tc358746_remove()
1608 pm_runtime_set_suspended(sd->dev); in tc358746_remove()
1609 pm_runtime_dont_use_autosuspend(sd->dev); in tc358746_remove()
1617 clk_disable_unprepare(tc358746->refclk); in tc358746_suspend()
1620 tc358746->supplies); in tc358746_suspend()
1622 clk_prepare_enable(tc358746->refclk); in tc358746_suspend()
1632 gpiod_set_value(tc358746->reset_gpio, 1); in tc358746_resume()
1635 tc358746->supplies); in tc358746_resume()
1642 gpiod_set_value(tc358746->reset_gpio, 0); in tc358746_resume()
1644 err = clk_prepare_enable(tc358746->refclk); in tc358746_resume()
1652 * Enable the PLL here since it can be called by the clk-framework or by in tc358746_resume()
1662 clk_disable_unprepare(tc358746->refclk); in tc358746_resume()
1665 tc358746->supplies); in tc358746_resume()
1690 MODULE_DESCRIPTION("Toshiba TC358746 Parallel to CSI-2 bridge driver");