Lines Matching +full:0 +full:x3b00

23 #define IMX415_PIXEL_ARRAY_TOP	  0
24 #define IMX415_PIXEL_ARRAY_LEFT 0
35 #define IMX415_REG_ADDR_MASK 0xffff
37 #define IMX415_MODE IMX415_REG_8BIT(0x3000)
38 #define IMX415_MODE_OPERATING (0)
39 #define IMX415_MODE_STANDBY BIT(0)
40 #define IMX415_REGHOLD IMX415_REG_8BIT(0x3001)
41 #define IMX415_REGHOLD_INVALID (0)
42 #define IMX415_REGHOLD_VALID BIT(0)
43 #define IMX415_XMSTA IMX415_REG_8BIT(0x3002)
44 #define IMX415_XMSTA_START (0)
45 #define IMX415_XMSTA_STOP BIT(0)
46 #define IMX415_BCWAIT_TIME IMX415_REG_16BIT(0x3008)
47 #define IMX415_CPWAIT_TIME IMX415_REG_16BIT(0x300A)
48 #define IMX415_WINMODE IMX415_REG_8BIT(0x301C)
49 #define IMX415_ADDMODE IMX415_REG_8BIT(0x3022)
50 #define IMX415_REVERSE IMX415_REG_8BIT(0x3030)
51 #define IMX415_HREVERSE_SHIFT (0)
52 #define IMX415_VREVERSE_SHIFT BIT(0)
53 #define IMX415_ADBIT IMX415_REG_8BIT(0x3031)
54 #define IMX415_MDBIT IMX415_REG_8BIT(0x3032)
55 #define IMX415_SYS_MODE IMX415_REG_8BIT(0x3033)
56 #define IMX415_OUTSEL IMX415_REG_8BIT(0x30C0)
57 #define IMX415_DRV IMX415_REG_8BIT(0x30C1)
58 #define IMX415_VMAX IMX415_REG_24BIT(0x3024)
59 #define IMX415_HMAX IMX415_REG_16BIT(0x3028)
60 #define IMX415_SHR0 IMX415_REG_24BIT(0x3050)
61 #define IMX415_GAIN_PCG_0 IMX415_REG_16BIT(0x3090)
62 #define IMX415_AGAIN_MIN 0
65 #define IMX415_BLKLEVEL IMX415_REG_16BIT(0x30E2)
67 #define IMX415_TPG_EN_DUOUT IMX415_REG_8BIT(0x30E4)
68 #define IMX415_TPG_PATSEL_DUOUT IMX415_REG_8BIT(0x30E6)
69 #define IMX415_TPG_COLORWIDTH IMX415_REG_8BIT(0x30E8)
70 #define IMX415_TESTCLKEN_MIPI IMX415_REG_8BIT(0x3110)
71 #define IMX415_INCKSEL1 IMX415_REG_8BIT(0x3115)
72 #define IMX415_INCKSEL2 IMX415_REG_8BIT(0x3116)
73 #define IMX415_INCKSEL3 IMX415_REG_16BIT(0x3118)
74 #define IMX415_INCKSEL4 IMX415_REG_16BIT(0x311A)
75 #define IMX415_INCKSEL5 IMX415_REG_8BIT(0x311E)
76 #define IMX415_DIG_CLP_MODE IMX415_REG_8BIT(0x32C8)
77 #define IMX415_WRJ_OPEN IMX415_REG_8BIT(0x3390)
78 #define IMX415_SENSOR_INFO IMX415_REG_16BIT(0x3F12)
79 #define IMX415_SENSOR_INFO_MASK 0xFFF
80 #define IMX415_CHIP_ID 0x514
81 #define IMX415_LANEMODE IMX415_REG_16BIT(0x4001)
84 #define IMX415_TXCLKESC_FREQ IMX415_REG_16BIT(0x4004)
85 #define IMX415_INCKSEL6 IMX415_REG_8BIT(0x400C)
86 #define IMX415_TCLKPOST IMX415_REG_16BIT(0x4018)
87 #define IMX415_TCLKPREPARE IMX415_REG_16BIT(0x401A)
88 #define IMX415_TCLKTRAIL IMX415_REG_16BIT(0x401C)
89 #define IMX415_TCLKZERO IMX415_REG_16BIT(0x401E)
90 #define IMX415_THSPREPARE IMX415_REG_16BIT(0x4020)
91 #define IMX415_THSZERO IMX415_REG_16BIT(0x4022)
92 #define IMX415_THSTRAIL IMX415_REG_16BIT(0x4024)
93 #define IMX415_THSEXIT IMX415_REG_16BIT(0x4026)
94 #define IMX415_TLPX IMX415_REG_16BIT(0x4028)
95 #define IMX415_INCKSEL7 IMX415_REG_8BIT(0x4074)
129 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
130 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
131 .regs[2] = { IMX415_SYS_MODE, 0x7 },
132 .regs[3] = { IMX415_INCKSEL1, 0x00 },
133 .regs[4] = { IMX415_INCKSEL2, 0x23 },
134 .regs[5] = { IMX415_INCKSEL3, 0x084 },
135 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
136 .regs[7] = { IMX415_INCKSEL5, 0x23 },
137 .regs[8] = { IMX415_INCKSEL6, 0x0 },
138 .regs[9] = { IMX415_INCKSEL7, 0x1 },
139 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
144 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
145 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
146 .regs[2] = { IMX415_SYS_MODE, 0x9 },
147 .regs[3] = { IMX415_INCKSEL1, 0x00 },
148 .regs[4] = { IMX415_INCKSEL2, 0x23 },
149 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },
150 .regs[6] = { IMX415_INCKSEL4, 0x0FC },
151 .regs[7] = { IMX415_INCKSEL5, 0x23 },
152 .regs[8] = { IMX415_INCKSEL6, 0x0 },
153 .regs[9] = { IMX415_INCKSEL7, 0x1 },
154 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
159 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
160 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
161 .regs[2] = { IMX415_SYS_MODE, 0x5 },
162 .regs[3] = { IMX415_INCKSEL1, 0x00 },
163 .regs[4] = { IMX415_INCKSEL2, 0x23 },
164 .regs[5] = { IMX415_INCKSEL3, 0x0C6 },
165 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
166 .regs[7] = { IMX415_INCKSEL5, 0x23 },
167 .regs[8] = { IMX415_INCKSEL6, 0x0 },
168 .regs[9] = { IMX415_INCKSEL7, 0x1 },
169 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
174 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
175 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
176 .regs[2] = { IMX415_SYS_MODE, 0x8 },
177 .regs[3] = { IMX415_INCKSEL1, 0x00 },
178 .regs[4] = { IMX415_INCKSEL2, 0x23 },
179 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },
180 .regs[6] = { IMX415_INCKSEL4, 0x0FC },
181 .regs[7] = { IMX415_INCKSEL5, 0x23 },
182 .regs[8] = { IMX415_INCKSEL6, 0x1 },
183 .regs[9] = { IMX415_INCKSEL7, 0x0 },
184 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
189 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
190 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
191 .regs[2] = { IMX415_SYS_MODE, 0x8 },
192 .regs[3] = { IMX415_INCKSEL1, 0x00 },
193 .regs[4] = { IMX415_INCKSEL2, 0x23 },
194 .regs[5] = { IMX415_INCKSEL3, 0x0A5 },
195 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
196 .regs[7] = { IMX415_INCKSEL5, 0x23 },
197 .regs[8] = { IMX415_INCKSEL6, 0x1 },
198 .regs[9] = { IMX415_INCKSEL7, 0x0 },
199 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
205 { IMX415_VMAX, 0x08CA },
206 { IMX415_HMAX, 0x07F0 },
208 { IMX415_TCLKPOST, 0x006F },
209 { IMX415_TCLKPREPARE, 0x002F },
210 { IMX415_TCLKTRAIL, 0x002F },
211 { IMX415_TCLKZERO, 0x00BF },
212 { IMX415_THSPREPARE, 0x002F },
213 { IMX415_THSZERO, 0x0057 },
214 { IMX415_THSTRAIL, 0x002F },
215 { IMX415_THSEXIT, 0x004F },
216 { IMX415_TLPX, 0x0027 },
221 { IMX415_VMAX, 0x08CA },
222 { IMX415_HMAX, 0x042A },
224 { IMX415_TCLKPOST, 0x009F },
225 { IMX415_TCLKPREPARE, 0x0057 },
226 { IMX415_TCLKTRAIL, 0x0057 },
227 { IMX415_TCLKZERO, 0x0187 },
228 { IMX415_THSPREPARE, 0x005F },
229 { IMX415_THSZERO, 0x00A7 },
230 { IMX415_THSTRAIL, 0x005F },
231 { IMX415_THSEXIT, 0x0097 },
232 { IMX415_TLPX, 0x004F },
237 { IMX415_VMAX, 0x08CA },
238 { IMX415_HMAX, 0x044C },
240 { IMX415_TCLKPOST, 0x007F },
241 { IMX415_TCLKPREPARE, 0x0037 },
242 { IMX415_TCLKTRAIL, 0x0037 },
243 { IMX415_TCLKZERO, 0x00F7 },
244 { IMX415_THSPREPARE, 0x003F },
245 { IMX415_THSZERO, 0x006F },
246 { IMX415_THSTRAIL, 0x003F },
247 { IMX415_THSEXIT, 0x005F },
248 { IMX415_TLPX, 0x002F },
376 { IMX415_WINMODE, 0x00 },
377 { IMX415_ADDMODE, 0x00 },
378 { IMX415_REVERSE, 0x00 },
380 { IMX415_ADBIT, 0x00 },
381 { IMX415_MDBIT, 0x00 },
383 { IMX415_OUTSEL, 0x22 },
384 { IMX415_DRV, 0x00 },
387 { IMX415_REG_8BIT(0x32D4), 0x21 },
388 { IMX415_REG_8BIT(0x32EC), 0xA1 },
389 { IMX415_REG_8BIT(0x3452), 0x7F },
390 { IMX415_REG_8BIT(0x3453), 0x03 },
391 { IMX415_REG_8BIT(0x358A), 0x04 },
392 { IMX415_REG_8BIT(0x35A1), 0x02 },
393 { IMX415_REG_8BIT(0x36BC), 0x0C },
394 { IMX415_REG_8BIT(0x36CC), 0x53 },
395 { IMX415_REG_8BIT(0x36CD), 0x00 },
396 { IMX415_REG_8BIT(0x36CE), 0x3C },
397 { IMX415_REG_8BIT(0x36D0), 0x8C },
398 { IMX415_REG_8BIT(0x36D1), 0x00 },
399 { IMX415_REG_8BIT(0x36D2), 0x71 },
400 { IMX415_REG_8BIT(0x36D4), 0x3C },
401 { IMX415_REG_8BIT(0x36D6), 0x53 },
402 { IMX415_REG_8BIT(0x36D7), 0x00 },
403 { IMX415_REG_8BIT(0x36D8), 0x71 },
404 { IMX415_REG_8BIT(0x36DA), 0x8C },
405 { IMX415_REG_8BIT(0x36DB), 0x00 },
406 { IMX415_REG_8BIT(0x3724), 0x02 },
407 { IMX415_REG_8BIT(0x3726), 0x02 },
408 { IMX415_REG_8BIT(0x3732), 0x02 },
409 { IMX415_REG_8BIT(0x3734), 0x03 },
410 { IMX415_REG_8BIT(0x3736), 0x03 },
411 { IMX415_REG_8BIT(0x3742), 0x03 },
412 { IMX415_REG_8BIT(0x3862), 0xE0 },
413 { IMX415_REG_8BIT(0x38CC), 0x30 },
414 { IMX415_REG_8BIT(0x38CD), 0x2F },
415 { IMX415_REG_8BIT(0x395C), 0x0C },
416 { IMX415_REG_8BIT(0x3A42), 0xD1 },
417 { IMX415_REG_8BIT(0x3A4C), 0x77 },
418 { IMX415_REG_8BIT(0x3AE0), 0x02 },
419 { IMX415_REG_8BIT(0x3AEC), 0x0C },
420 { IMX415_REG_8BIT(0x3B00), 0x2E },
421 { IMX415_REG_8BIT(0x3B06), 0x29 },
422 { IMX415_REG_8BIT(0x3B98), 0x25 },
423 { IMX415_REG_8BIT(0x3B99), 0x21 },
424 { IMX415_REG_8BIT(0x3B9B), 0x13 },
425 { IMX415_REG_8BIT(0x3B9C), 0x13 },
426 { IMX415_REG_8BIT(0x3B9D), 0x13 },
427 { IMX415_REG_8BIT(0x3B9E), 0x13 },
428 { IMX415_REG_8BIT(0x3BA1), 0x00 },
429 { IMX415_REG_8BIT(0x3BA2), 0x06 },
430 { IMX415_REG_8BIT(0x3BA3), 0x0B },
431 { IMX415_REG_8BIT(0x3BA4), 0x10 },
432 { IMX415_REG_8BIT(0x3BA5), 0x14 },
433 { IMX415_REG_8BIT(0x3BA6), 0x18 },
434 { IMX415_REG_8BIT(0x3BA7), 0x1A },
435 { IMX415_REG_8BIT(0x3BA8), 0x1A },
436 { IMX415_REG_8BIT(0x3BA9), 0x1A },
437 { IMX415_REG_8BIT(0x3BAC), 0xED },
438 { IMX415_REG_8BIT(0x3BAD), 0x01 },
439 { IMX415_REG_8BIT(0x3BAE), 0xF6 },
440 { IMX415_REG_8BIT(0x3BAF), 0x02 },
441 { IMX415_REG_8BIT(0x3BB0), 0xA2 },
442 { IMX415_REG_8BIT(0x3BB1), 0x03 },
443 { IMX415_REG_8BIT(0x3BB2), 0xE0 },
444 { IMX415_REG_8BIT(0x3BB3), 0x03 },
445 { IMX415_REG_8BIT(0x3BB4), 0xE0 },
446 { IMX415_REG_8BIT(0x3BB5), 0x03 },
447 { IMX415_REG_8BIT(0x3BB6), 0xE0 },
448 { IMX415_REG_8BIT(0x3BB7), 0x03 },
449 { IMX415_REG_8BIT(0x3BB8), 0xE0 },
450 { IMX415_REG_8BIT(0x3BBA), 0xE0 },
451 { IMX415_REG_8BIT(0x3BBC), 0xDA },
452 { IMX415_REG_8BIT(0x3BBE), 0x88 },
453 { IMX415_REG_8BIT(0x3BC0), 0x44 },
454 { IMX415_REG_8BIT(0x3BC2), 0x7B },
455 { IMX415_REG_8BIT(0x3BC4), 0xA2 },
456 { IMX415_REG_8BIT(0x3BC8), 0xBD },
457 { IMX415_REG_8BIT(0x3BCA), 0xBD },
467 u8 data[3] = { 0 }; in imx415_read()
472 if (ret < 0) in imx415_read()
475 return (data[2] << 16) | (data[1] << 8) | data[0]; in imx415_read()
480 u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 }; in imx415_write()
485 if (ret < 0) in imx415_write()
487 "%u-bit write to 0x%04x failed: %d\n", in imx415_write()
491 return 0; in imx415_write()
499 ret = imx415_write(sensor, IMX415_BLKLEVEL, 0x00); in imx415_set_testpattern()
502 ret = imx415_write(sensor, IMX415_TPG_EN_DUOUT, 0x01); in imx415_set_testpattern()
508 ret = imx415_write(sensor, IMX415_TPG_COLORWIDTH, 0x01); in imx415_set_testpattern()
511 ret = imx415_write(sensor, IMX415_TESTCLKEN_MIPI, 0x20); in imx415_set_testpattern()
514 ret = imx415_write(sensor, IMX415_DIG_CLP_MODE, 0x00); in imx415_set_testpattern()
517 ret = imx415_write(sensor, IMX415_WRJ_OPEN, 0x00); in imx415_set_testpattern()
523 ret = imx415_write(sensor, IMX415_TPG_EN_DUOUT, 0x00); in imx415_set_testpattern()
526 ret = imx415_write(sensor, IMX415_TESTCLKEN_MIPI, 0x00); in imx415_set_testpattern()
529 ret = imx415_write(sensor, IMX415_DIG_CLP_MODE, 0x01); in imx415_set_testpattern()
532 ret = imx415_write(sensor, IMX415_WRJ_OPEN, 0x01); in imx415_set_testpattern()
534 return 0; in imx415_set_testpattern()
547 return 0; in imx415_s_ctrl()
550 format = v4l2_subdev_get_pad_format(&sensor->subdev, state, 0); in imx415_s_ctrl()
594 if (ret < 0) in imx415_ctrls_init()
599 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); ++i) { in imx415_ctrls_init()
649 V4L2_CID_HFLIP, 0, 1, 1, 0); in imx415_ctrls_init()
651 V4L2_CID_VFLIP, 0, 1, 1, 0); in imx415_ctrls_init()
656 0, 0, imx415_test_pattern_menu); in imx415_ctrls_init()
669 return 0; in imx415_ctrls_init()
676 int ret = 0; in imx415_set_mode()
683 for (i = 0; i < supported_modes[mode].reg_list.num_of_regs; ++i) { in imx415_set_mode()
690 for (i = 0; i < IMX415_NUM_CLK_PARAM_REGS; ++i) { in imx415_set_mode()
697 return 0; in imx415_set_mode()
705 for (i = 0; i < ARRAY_SIZE(imx415_init_table); ++i) { in imx415_setup()
730 return 0; in imx415_wakeup()
775 if (ret < 0) in imx415_s_stream()
790 if (ret < 0) in imx415_s_stream()
797 ret = 0; in imx415_s_stream()
819 if (code->index != 0) in imx415_enum_mbus_code()
824 return 0; in imx415_enum_mbus_code()
835 if (fse->index > 0 || fse->code != format->code) in imx415_enum_frame_size()
842 return 0; in imx415_enum_frame_size()
851 return 0; in imx415_get_format()
872 return 0; in imx415_set_format()
888 return 0; in imx415_get_selection()
906 return 0; in imx415_init_cfg()
943 if (ret < 0) { in imx415_subdev_init()
951 return 0; in imx415_subdev_init()
966 if (ret < 0) in imx415_power_on()
969 gpiod_set_value_cansleep(sensor->reset, 0); in imx415_power_on()
974 if (ret < 0) in imx415_power_on()
984 return 0; in imx415_power_on()
1013 if (ret < 0) { in imx415_identify_model()
1027 "invalid device model 0x%04x\n", model); in imx415_identify_model()
1031 ret = 0; in imx415_identify_model()
1042 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) { in imx415_check_inck()
1051 return 0; in imx415_check_inck()
1065 for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i) in imx415_parse_hw_config()
1117 for (i = 0; i < bus_cfg.nr_of_link_frequencies; ++i) { in imx415_parse_hw_config()
1125 for (j = 0; j < ARRAY_SIZE(supported_modes); ++j) { in imx415_parse_hw_config()
1144 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) { in imx415_parse_hw_config()
1158 ret = 0; in imx415_parse_hw_config()
1213 if (ret < 0) in imx415_probe()
1225 return 0; in imx415_probe()
1272 return 0; in imx415_runtime_suspend()