Lines Matching refs:IMX296_REG_8BIT
26 #define IMX296_REG_8BIT(n) ((1 << 16) | (n)) macro
32 #define IMX296_CTRL00 IMX296_REG_8BIT(0x3000)
34 #define IMX296_CTRL08 IMX296_REG_8BIT(0x3008)
36 #define IMX296_CTRL0A IMX296_REG_8BIT(0x300a)
38 #define IMX296_CTRL0B IMX296_REG_8BIT(0x300b)
40 #define IMX296_CTRL0D IMX296_REG_8BIT(0x300d)
45 #define IMX296_CTRL0E IMX296_REG_8BIT(0x300e)
50 #define IMX296_TMDCTRL IMX296_REG_8BIT(0x301d)
54 #define IMX296_WDSEL IMX296_REG_8BIT(0x3021)
58 #define IMX296_BLKLEVELAUTO IMX296_REG_8BIT(0x3022)
61 #define IMX296_SST IMX296_REG_8BIT(0x3024)
63 #define IMX296_CTRLTOUT IMX296_REG_8BIT(0x3026)
68 #define IMX296_CTRLTRIG IMX296_REG_8BIT(0x3029)
73 #define IMX296_SYNCSEL IMX296_REG_8BIT(0x3036)
76 #define IMX296_PULSE1 IMX296_REG_8BIT(0x306d)
83 #define IMX296_PULSE2 IMX296_REG_8BIT(0x3079)
90 #define IMX296_INCKSEL(n) IMX296_REG_8BIT(0x3089 + (n))
95 #define IMX296_VBLANKLP IMX296_REG_8BIT(0x309c)
98 #define IMX296_EXP_CNT IMX296_REG_8BIT(0x30a3)
101 #define IMX296_VINT IMX296_REG_8BIT(0x30aa)
103 #define IMX296_LOWLAGTRG IMX296_REG_8BIT(0x30ae)
105 #define IMX296_I2CCTRL IMX296_REG_8BIT(0x30ef)
119 #define IMX296_GAINCTRL IMX296_REG_8BIT(0x3200)
128 #define IMX296_GAINDLY IMX296_REG_8BIT(0x3212)
131 #define IMX296_PGCTRL IMX296_REG_8BIT(0x3238)
138 #define IMX296_PGHPSTEP IMX296_REG_8BIT(0x323e)
139 #define IMX296_PGVPSTEP IMX296_REG_8BIT(0x323f)
140 #define IMX296_PGHPNUM IMX296_REG_8BIT(0x3240)
141 #define IMX296_PGVPNUM IMX296_REG_8BIT(0x3241)
144 #define IMX296_PGHGSTEP IMX296_REG_8BIT(0x3249)
147 #define IMX296_FID0_ROI IMX296_REG_8BIT(0x3300)
163 #define IMX296_SST_SIEASTA1_SET IMX296_REG_8BIT(0x40c9)
168 #define IMX296_HSST IMX296_REG_8BIT(0x40dc)
171 #define IMX296_CKREQSEL IMX296_REG_8BIT(0x4101)
173 #define IMX296_GTTABLENUM IMX296_REG_8BIT(0x4114)
174 #define IMX296_CTRL418C IMX296_REG_8BIT(0x418c)
464 { IMX296_REG_8BIT(0x3005), 0xf0 },
465 { IMX296_REG_8BIT(0x309e), 0x04 },
466 { IMX296_REG_8BIT(0x30a0), 0x04 },
467 { IMX296_REG_8BIT(0x30a1), 0x3c },
468 { IMX296_REG_8BIT(0x30a4), 0x5f },
469 { IMX296_REG_8BIT(0x30a8), 0x91 },
470 { IMX296_REG_8BIT(0x30ac), 0x28 },
471 { IMX296_REG_8BIT(0x30af), 0x09 },
472 { IMX296_REG_8BIT(0x30df), 0x00 },
473 { IMX296_REG_8BIT(0x3165), 0x00 },
474 { IMX296_REG_8BIT(0x3169), 0x10 },
475 { IMX296_REG_8BIT(0x316a), 0x02 },
476 { IMX296_REG_8BIT(0x31c8), 0xf3 }, /* Exposure-related */
477 { IMX296_REG_8BIT(0x31d0), 0xf4 }, /* Exposure-related */
478 { IMX296_REG_8BIT(0x321a), 0x00 },
479 { IMX296_REG_8BIT(0x3226), 0x02 },
480 { IMX296_REG_8BIT(0x3256), 0x01 },
481 { IMX296_REG_8BIT(0x3541), 0x72 },
482 { IMX296_REG_8BIT(0x3516), 0x77 },
483 { IMX296_REG_8BIT(0x350b), 0x7f },
484 { IMX296_REG_8BIT(0x3758), 0xa3 },
485 { IMX296_REG_8BIT(0x3759), 0x00 },
486 { IMX296_REG_8BIT(0x375a), 0x85 },
487 { IMX296_REG_8BIT(0x375b), 0x00 },
488 { IMX296_REG_8BIT(0x3832), 0xf5 },
489 { IMX296_REG_8BIT(0x3833), 0x00 },
490 { IMX296_REG_8BIT(0x38a2), 0xf6 },
491 { IMX296_REG_8BIT(0x38a3), 0x00 },
492 { IMX296_REG_8BIT(0x3a00), 0x80 },
493 { IMX296_REG_8BIT(0x3d48), 0xa3 },
494 { IMX296_REG_8BIT(0x3d49), 0x00 },
495 { IMX296_REG_8BIT(0x3d4a), 0x85 },
496 { IMX296_REG_8BIT(0x3d4b), 0x00 },
497 { IMX296_REG_8BIT(0x400e), 0x58 },
498 { IMX296_REG_8BIT(0x4014), 0x1c },
499 { IMX296_REG_8BIT(0x4041), 0x2a },
500 { IMX296_REG_8BIT(0x40a2), 0x06 },
501 { IMX296_REG_8BIT(0x40c1), 0xf6 },
502 { IMX296_REG_8BIT(0x40c7), 0x0f },
503 { IMX296_REG_8BIT(0x40c8), 0x00 },
504 { IMX296_REG_8BIT(0x4174), 0x00 },