82 static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data)  in ves1x93_writereg()  function
114 	ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);  in ves1x93_clr_bit()
115 	ves1x93_writereg (state, 0, state->init_1x93_tab[0]);  in ves1x93_clr_bit()
144 	return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val);  in ves1x93_set_inversion()
150 		return ves1x93_writereg (state, 0x0d, 0x08);  in ves1x93_set_fec()
154 		return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);  in ves1x93_set_fec()
226 	ves1x93_writereg (state, 0x06, 0xff & BDR);  in ves1x93_set_symbolrate()
227 	ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));  in ves1x93_set_symbolrate()
228 	ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));  in ves1x93_set_symbolrate()
230 	ves1x93_writereg (state, 0x09, BDRI);  in ves1x93_set_symbolrate()
231 	ves1x93_writereg (state, 0x20, ADCONF);  in ves1x93_set_symbolrate()
232 	ves1x93_writereg (state, 0x21, FCONF);  in ves1x93_set_symbolrate()
243 	ves1x93_writereg (state, 0x05, AGCR);  in ves1x93_set_symbolrate()
265 			ves1x93_writereg (state, i, val);  in ves1x93_init()
279 		return ves1x93_writereg (state, 0x1f, 0x20);  in ves1x93_set_voltage()
281 		return ves1x93_writereg (state, 0x1f, 0x30);  in ves1x93_set_voltage()
283 		return ves1x93_writereg (state, 0x1f, 0x00);  in ves1x93_set_voltage()
372 	ves1x93_writereg (state, 0x18, 0x00);  /* reset the counter */  in ves1x93_read_ucblocks()
373 	ves1x93_writereg (state, 0x18, 0x80);  /* dto. */  in ves1x93_read_ucblocks()
424 	return ves1x93_writereg (state, 0x00, 0x08);  in ves1x93_sleep()
438 		return ves1x93_writereg(state, 0x00, 0x11);  in ves1x93_i2c_gate_ctrl()
440 		return ves1x93_writereg(state, 0x00, 0x01);  in ves1x93_i2c_gate_ctrl()