47 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)  in ves1820_writereg()  function
94 	ves1820_writereg(state, 0x00, reg0 & 0xfe);  in ves1820_setup_reg0()
95 	ves1820_writereg(state, 0x00, reg0 | 0x01);  in ves1820_setup_reg0()
169 	ves1820_writereg(state, 0x03, NDEC);  in ves1820_set_symbolrate()
170 	ves1820_writereg(state, 0x0a, BDR & 0xff);  in ves1820_set_symbolrate()
171 	ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);  in ves1820_set_symbolrate()
172 	ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);  in ves1820_set_symbolrate()
174 	ves1820_writereg(state, 0x0d, BDRI);  in ves1820_set_symbolrate()
175 	ves1820_writereg(state, 0x0e, SFIL);  in ves1820_set_symbolrate()
185 	ves1820_writereg(state, 0, 0);  in ves1820_init()
188 		ves1820_writereg(state, i, ves1820_inittab[i]);  in ves1820_init()
190 		ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);  in ves1820_init()
192 	ves1820_writereg(state, 0x34, state->pwm);  in ves1820_init()
217 	ves1820_writereg(state, 0x34, state->pwm);  in ves1820_set_parameters()
219 	ves1820_writereg(state, 0x01, reg0x01[real_qam]);  in ves1820_set_parameters()
220 	ves1820_writereg(state, 0x05, reg0x05[real_qam]);  in ves1820_set_parameters()
221 	ves1820_writereg(state, 0x08, reg0x08[real_qam]);  in ves1820_set_parameters()
222 	ves1820_writereg(state, 0x09, reg0x09[real_qam]);  in ves1820_set_parameters()
225 	ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));  in ves1820_set_parameters()
297 	ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);  in ves1820_read_ucblocks()
298 	ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);  in ves1820_read_ucblocks()
339 	ves1820_writereg(state, 0x1b, 0x02);	/* pdown ADC */  in ves1820_sleep()
340 	ves1820_writereg(state, 0x00, 0x80);	/* standby */  in ves1820_sleep()