Lines Matching refs:tda1004x_write_byteI
115 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) in tda1004x_write_byteI() function
176 return tda1004x_write_byteI(state, reg, val); in tda1004x_write_mask()
188 result = tda1004x_write_byteI(state, reg + i, buf[i]); in tda1004x_write_buf()
237 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0); in tda10045h_set_bandwidth()
268 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); in tda10046h_set_bandwidth()
269 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab); in tda10046h_set_bandwidth()
281 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); in tda10046h_set_bandwidth()
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); in tda10046h_set_bandwidth()
294 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); in tda10046h_set_bandwidth()
295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55); in tda10046h_set_bandwidth()
316 tda1004x_write_byteI(state, dspCodeCounterReg, 0); in tda1004x_do_upload()
366 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67); in tda1004x_check_upload_ok()
429 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); in tda10046_init_plls()
432 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8 in tda10046_init_plls()
435 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3 in tda10046_init_plls()
439 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 in tda10046_init_plls()
442 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 in tda10046_init_plls()
445 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67); in tda10046_init_plls()
447 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72); in tda10046_init_plls()
451 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); in tda10046_init_plls()
452 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); in tda10046_init_plls()
455 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); in tda10046_init_plls()
456 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7); in tda10046_init_plls()
459 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); in tda10046_init_plls()
460 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59); in tda10046_init_plls()
463 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); in tda10046_init_plls()
464 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); in tda10046_init_plls()
485 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); in tda10046_fwupload()
490 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33); in tda10046_fwupload()
517 tda1004x_write_byteI(state, TDA1004X_CONFC4, 4); in tda10046_fwupload()
519 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); in tda10046_fwupload()
599 return tda1004x_write_byteI(state, buf[0], buf[1]); in tda1004x_write()
622 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface in tda10045_init()
623 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface in tda10045_init()
626 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e); in tda10045_init()
645 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream in tda10046_init()
646 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer in tda10046_init()
650 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup in tda10046_init()
654 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup in tda10046_init()
658 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup in tda10046_init()
662 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup in tda10046_init()
663 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold in tda10046_init()
664 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize in tda10046_init()
676 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38); in tda10046_init()
678 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } in tda10046_init()
679 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values in tda10046_init()
680 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } in tda10046_init()
681 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } in tda10046_init()
682 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1 in tda10046_init()
683 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits in tda10046_init()
684 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config in tda10046_init()
685 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config in tda10046_init()
1194 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff); in tda1004x_sleep()