124 static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val)  in si2165_writereg8()  function
168 	return si2165_writereg8(state, reg, val);  in si2165_writereg_mask8()
187 		ret = si2165_writereg8(state, regs[i].reg, regs[i].val);  in si2165_write_reg_list()
258 	return si2165_writereg8(state, REG_PLL_DIVL, divl);  in si2165_adjust_pll_divl()
426 	ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);  in si2165_upload_firmware()
430 	ret = si2165_writereg8(state, REG_RST_ALL, 0x00);  in si2165_upload_firmware()
445 	ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02);  in si2165_upload_firmware()
459 	ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version);  in si2165_upload_firmware()
464 	ret = si2165_writereg8(state, REG_RST_CRC, 0x01);  in si2165_upload_firmware()
535 	ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);  in si2165_init()
539 	ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01);  in si2165_init()
552 	ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00);  in si2165_init()
555 	ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01);  in si2165_init()
558 	ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00);  in si2165_init()
561 	ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07);  in si2165_init()
565 	ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00);  in si2165_init()
568 	ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00);  in si2165_init()
577 	ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01);  in si2165_init()
581 	ret = si2165_writereg8(state, REG_START_INIT, 0x01);  in si2165_init()
589 	ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00);  in si2165_init()
603 	ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00);  in si2165_init()
623 	ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20);  in si2165_init()
632 	ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01);  in si2165_init()
635 	ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00);  in si2165_init()
658 	ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00);  in si2165_sleep()
662 	ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);  in si2165_sleep()
746 			ret = si2165_writereg8(state, REG_BER_RST, 0x01);  in si2165_read_status()
781 				ret = si2165_writereg8(state,  in si2165_read_status()
1010 	ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp);  in si2165_set_frontend_dvbc()
1078 	ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);  in si2165_set_frontend()
1083 	ret = si2165_writereg8(state, REG_RST_ALL, 0x00);  in si2165_set_frontend()
1098 	ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01);  in si2165_set_frontend()
1199 	ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);  in si2165_probe()
1218 	ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);  in si2165_probe()