Lines Matching refs:s5h1420_writereg
96 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data) in s5h1420_writereg() function
122 s5h1420_writereg(state, 0x3c, in s5h1420_set_voltage()
127 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03); in s5h1420_set_voltage()
131 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd); in s5h1420_set_voltage()
147 s5h1420_writereg(state, 0x3b, in s5h1420_set_tone()
152 s5h1420_writereg(state, 0x3b, in s5h1420_set_tone()
176 s5h1420_writereg(state, 0x3b, 0x02); in s5h1420_send_master_cmd()
181 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]); in s5h1420_send_master_cmd()
185 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | in s5h1420_send_master_cmd()
200 s5h1420_writereg(state, 0x3b, val); in s5h1420_send_master_cmd()
218 …s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive … in s5h1420_recv_slave_reply()
256 s5h1420_writereg(state, 0x3b, val); in s5h1420_recv_slave_reply()
271 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01); in s5h1420_send_burst()
275 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04); in s5h1420_send_burst()
280 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08); in s5h1420_send_burst()
294 s5h1420_writereg(state, 0x3b, val); in s5h1420_send_burst()
340 s5h1420_writereg(state, Vit09, 0x13); in s5h1420_read_status()
342 s5h1420_writereg(state, Vit09, 0x1b); in s5h1420_read_status()
390 s5h1420_writereg(state, FEC01, 0x18); in s5h1420_read_status()
391 s5h1420_writereg(state, FEC01, 0x10); in s5h1420_read_status()
392 s5h1420_writereg(state, FEC01, val); in s5h1420_read_status()
396 s5h1420_writereg(state, Mpeg02, val | (1 << 6)); in s5h1420_read_status()
400 s5h1420_writereg(state, QPSK01, val); in s5h1420_read_status()
405 s5h1420_writereg(state, Loop04, 0x8a); in s5h1420_read_status()
406 s5h1420_writereg(state, Loop05, 0x6a); in s5h1420_read_status()
408 s5h1420_writereg(state, Loop04, 0x58); in s5h1420_read_status()
409 s5h1420_writereg(state, Loop05, 0x27); in s5h1420_read_status()
425 s5h1420_writereg(state, 0x46, 0x1d); in s5h1420_read_ber()
448 s5h1420_writereg(state, 0x46, 0x1f); in s5h1420_read_ucblocks()
459 s5h1420_writereg (state, 0x01, 0x08); in s5h1420_reset()
460 s5h1420_writereg (state, 0x01, 0x00); in s5h1420_reset()
480 s5h1420_writereg(state, Loop01, v & 0x7f); in s5h1420_setsymbolrate()
481 s5h1420_writereg(state, Tnco01, val >> 16); in s5h1420_setsymbolrate()
482 s5h1420_writereg(state, Tnco02, val >> 8); in s5h1420_setsymbolrate()
483 s5h1420_writereg(state, Tnco03, val & 0xff); in s5h1420_setsymbolrate()
484 s5h1420_writereg(state, Loop01, v | 0x80); in s5h1420_setsymbolrate()
507 s5h1420_writereg(state, Loop01, v & 0xbf); in s5h1420_setfreqoffset()
508 s5h1420_writereg(state, Pnco01, val >> 16); in s5h1420_setfreqoffset()
509 s5h1420_writereg(state, Pnco02, val >> 8); in s5h1420_setfreqoffset()
510 s5h1420_writereg(state, Pnco03, val & 0xff); in s5h1420_setfreqoffset()
511 s5h1420_writereg(state, Loop01, v | 0x40); in s5h1420_setfreqoffset()
519 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08); in s5h1420_getfreqoffset()
523 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7); in s5h1420_getfreqoffset()
589 s5h1420_writereg(state, Vit08, vit08); in s5h1420_setfec_inversion()
590 s5h1420_writereg(state, Vit09, vit09); in s5h1420_setfec_inversion()
679 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8); in s5h1420_set_frontend()
680 s5h1420_writereg(state, PLL02, 0x40); in s5h1420_set_frontend()
681 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); in s5h1420_set_frontend()
685 s5h1420_writereg(state, QPSK01, 0xae | 0x10); in s5h1420_set_frontend()
687 s5h1420_writereg(state, QPSK01, 0xac | 0x10); in s5h1420_set_frontend()
690 s5h1420_writereg(state, CON_1, 0x00); in s5h1420_set_frontend()
691 s5h1420_writereg(state, QPSK02, 0x00); in s5h1420_set_frontend()
692 s5h1420_writereg(state, Pre01, 0xb0); in s5h1420_set_frontend()
694 s5h1420_writereg(state, Loop01, 0xF0); in s5h1420_set_frontend()
695 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */ in s5h1420_set_frontend()
696 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */ in s5h1420_set_frontend()
698 s5h1420_writereg(state, Loop04, 0x79); in s5h1420_set_frontend()
700 s5h1420_writereg(state, Loop04, 0x58); in s5h1420_set_frontend()
701 s5h1420_writereg(state, Loop05, 0x6b); in s5h1420_set_frontend()
704 s5h1420_writereg(state, Post01, (0 << 6) | 0x10); in s5h1420_set_frontend()
706 s5h1420_writereg(state, Post01, (1 << 6) | 0x10); in s5h1420_set_frontend()
708 s5h1420_writereg(state, Post01, (3 << 6) | 0x10); in s5h1420_set_frontend()
710 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */ in s5h1420_set_frontend()
712 s5h1420_writereg(state, Sync01, 0x33); in s5h1420_set_frontend()
713 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity); in s5h1420_set_frontend()
714 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */ in s5h1420_set_frontend()
715 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */ in s5h1420_set_frontend()
717 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */ in s5h1420_set_frontend()
718 s5h1420_writereg(state, DiS03, 0x00); in s5h1420_set_frontend()
719 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */ in s5h1420_set_frontend()
734 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1); in s5h1420_set_frontend()
796 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1); in s5h1420_i2c_gate_ctrl()
798 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe); in s5h1420_i2c_gate_ctrl()
807 s5h1420_writereg(state, 0x02, state->CON_1_val); in s5h1420_init()
818 return s5h1420_writereg(state, 0x02, state->CON_1_val); in s5h1420_sleep()