14 	[DVBT_SOFT_RST]		= {0x101,  2, 2},
15 	[DVBT_IIC_REPEAT]	= {0x101,  3, 3},
16 	[DVBT_TR_WAIT_MIN_8K]	= {0x188, 11, 2},
17 	[DVBT_RSD_BER_FAIL_VAL]	= {0x18f, 15, 0},
18 	[DVBT_EN_BK_TRK]	= {0x1a6,  7, 7},
19 	[DVBT_AD_EN_REG]	= {0x008,  7, 7},
20 	[DVBT_AD_EN_REG1]	= {0x008,  6, 6},
21 	[DVBT_EN_BBIN]		= {0x1b1,  0, 0},
22 	[DVBT_MGD_THD0]		= {0x195,  7, 0},
23 	[DVBT_MGD_THD1]		= {0x196,  7, 0},
24 	[DVBT_MGD_THD2]		= {0x197,  7, 0},
25 	[DVBT_MGD_THD3]		= {0x198,  7, 0},
26 	[DVBT_MGD_THD4]		= {0x199,  7, 0},
27 	[DVBT_MGD_THD5]		= {0x19a,  7, 0},
28 	[DVBT_MGD_THD6]		= {0x19b,  7, 0},
29 	[DVBT_MGD_THD7]		= {0x19c,  7, 0},
30 	[DVBT_EN_CACQ_NOTCH]	= {0x161,  4, 4},
31 	[DVBT_AD_AV_REF]	= {0x009,  6, 0},
32 	[DVBT_REG_PI]		= {0x00a,  2, 0},
33 	[DVBT_PIP_ON]		= {0x021,  3, 3},
34 	[DVBT_SCALE1_B92]	= {0x292,  7, 0},
35 	[DVBT_SCALE1_B93]	= {0x293,  7, 0},
36 	[DVBT_SCALE1_BA7]	= {0x2a7,  7, 0},
37 	[DVBT_SCALE1_BA9]	= {0x2a9,  7, 0},
38 	[DVBT_SCALE1_BAA]	= {0x2aa,  7, 0},
39 	[DVBT_SCALE1_BAB]	= {0x2ab,  7, 0},
40 	[DVBT_SCALE1_BAC]	= {0x2ac,  7, 0},
41 	[DVBT_SCALE1_BB0]	= {0x2b0,  7, 0},
42 	[DVBT_SCALE1_BB1]	= {0x2b1,  7, 0},
43 	[DVBT_KB_P1]		= {0x164,  3, 1},
44 	[DVBT_KB_P2]		= {0x164,  6, 4},
45 	[DVBT_KB_P3]		= {0x165,  2, 0},
46 	[DVBT_OPT_ADC_IQ]	= {0x006,  5, 4},
47 	[DVBT_AD_AVI]		= {0x009,  1, 0},
48 	[DVBT_AD_AVQ]		= {0x009,  3, 2},
49 	[DVBT_K1_CR_STEP12]	= {0x2ad,  9, 4},
50 	[DVBT_TRK_KS_P2]	= {0x16f,  2, 0},
51 	[DVBT_TRK_KS_I2]	= {0x170,  5, 3},
52 	[DVBT_TR_THD_SET2]	= {0x172,  3, 0},
53 	[DVBT_TRK_KC_P2]	= {0x173,  5, 3},
54 	[DVBT_TRK_KC_I2]	= {0x175,  2, 0},
55 	[DVBT_CR_THD_SET2]	= {0x176,  7, 6},
56 	[DVBT_PSET_IFFREQ]	= {0x119, 21, 0},
57 	[DVBT_SPEC_INV]		= {0x115,  0, 0},
58 	[DVBT_RSAMP_RATIO]	= {0x19f, 27, 2},
59 	[DVBT_CFREQ_OFF_RATIO]	= {0x19d, 23, 4},
60 	[DVBT_FSM_STAGE]	= {0x351,  6, 3},
61 	[DVBT_RX_CONSTEL]	= {0x33c,  3, 2},
62 	[DVBT_RX_HIER]		= {0x33c,  6, 4},
63 	[DVBT_RX_C_RATE_LP]	= {0x33d,  2, 0},
64 	[DVBT_RX_C_RATE_HP]	= {0x33d,  5, 3},
65 	[DVBT_GI_IDX]		= {0x351,  1, 0},
66 	[DVBT_FFT_MODE_IDX]	= {0x351,  2, 2},
67 	[DVBT_RSD_BER_EST]	= {0x34e, 15, 0},
68 	[DVBT_CE_EST_EVM]	= {0x40c, 15, 0},
69 	[DVBT_RF_AGC_VAL]	= {0x35b, 13, 0},
70 	[DVBT_IF_AGC_VAL]	= {0x359, 13, 0},
71 	[DVBT_DAGC_VAL]		= {0x305,  7, 0},
72 	[DVBT_SFREQ_OFF]	= {0x318, 13, 0},
73 	[DVBT_CFREQ_OFF]	= {0x35f, 17, 0},
74 	[DVBT_POLAR_RF_AGC]	= {0x00e,  1, 1},
75 	[DVBT_POLAR_IF_AGC]	= {0x00e,  0, 0},
76 	[DVBT_AAGC_HOLD]	= {0x104,  5, 5},
77 	[DVBT_EN_RF_AGC]	= {0x104,  6, 6},
78 	[DVBT_EN_IF_AGC]	= {0x104,  7, 7},
79 	[DVBT_IF_AGC_MIN]	= {0x108,  7, 0},
80 	[DVBT_IF_AGC_MAX]	= {0x109,  7, 0},
81 	[DVBT_RF_AGC_MIN]	= {0x10a,  7, 0},
82 	[DVBT_RF_AGC_MAX]	= {0x10b,  7, 0},
83 	[DVBT_IF_AGC_MAN]	= {0x10c,  6, 6},
84 	[DVBT_IF_AGC_MAN_VAL]	= {0x10c, 13, 0},
85 	[DVBT_RF_AGC_MAN]	= {0x10e,  6, 6},
86 	[DVBT_RF_AGC_MAN_VAL]	= {0x10e, 13, 0},
87 	[DVBT_DAGC_TRG_VAL]	= {0x112,  7, 0},
88 	[DVBT_AGC_TARG_VAL_0]	= {0x102,  0, 0},
89 	[DVBT_AGC_TARG_VAL_8_1]	= {0x103,  7, 0},
90 	[DVBT_AAGC_LOOP_GAIN]	= {0x1c7,  5, 1},
91 	[DVBT_LOOP_GAIN2_3_0]	= {0x104,  4, 1},
92 	[DVBT_LOOP_GAIN2_4]	= {0x105,  7, 7},
93 	[DVBT_LOOP_GAIN3]	= {0x1c8,  4, 0},
94 	[DVBT_VTOP1]		= {0x106,  5, 0},
95 	[DVBT_VTOP2]		= {0x1c9,  5, 0},
96 	[DVBT_VTOP3]		= {0x1ca,  5, 0},
97 	[DVBT_KRF1]		= {0x1cb,  7, 0},
98 	[DVBT_KRF2]		= {0x107,  7, 0},
99 	[DVBT_KRF3]		= {0x1cd,  7, 0},
100 	[DVBT_KRF4]		= {0x1ce,  7, 0},
101 	[DVBT_EN_GI_PGA]	= {0x1e5,  0, 0},
102 	[DVBT_THD_LOCK_UP]	= {0x1d9,  8, 0},
103 	[DVBT_THD_LOCK_DW]	= {0x1db,  8, 0},
104 	[DVBT_THD_UP1]		= {0x1dd,  7, 0},
105 	[DVBT_THD_DW1]		= {0x1de,  7, 0},
106 	[DVBT_INTER_CNT_LEN]	= {0x1d8,  3, 0},
107 	[DVBT_GI_PGA_STATE]	= {0x1e6,  3, 3},
108 	[DVBT_EN_AGC_PGA]	= {0x1d7,  0, 0},
109 	[DVBT_CKOUTPAR]		= {0x17b,  5, 5},
110 	[DVBT_CKOUT_PWR]	= {0x17b,  6, 6},
111 	[DVBT_SYNC_DUR]		= {0x17b,  7, 7},
112 	[DVBT_ERR_DUR]		= {0x17c,  0, 0},
113 	[DVBT_SYNC_LVL]		= {0x17c,  1, 1},
114 	[DVBT_ERR_LVL]		= {0x17c,  2, 2},
115 	[DVBT_VAL_LVL]		= {0x17c,  3, 3},
116 	[DVBT_SERIAL]		= {0x17c,  4, 4},
117 	[DVBT_SER_LSB]		= {0x17c,  5, 5},
118 	[DVBT_CDIV_PH0]		= {0x17d,  3, 0},
119 	[DVBT_CDIV_PH1]		= {0x17d,  7, 4},
120 	[DVBT_MPEG_IO_OPT_2_2]	= {0x006,  7, 7},
121 	[DVBT_MPEG_IO_OPT_1_0]	= {0x007,  7, 6},
122 	[DVBT_CKOUTPAR_PIP]	= {0x0b7,  4, 4},
123 	[DVBT_CKOUT_PWR_PIP]	= {0x0b7,  3, 3},
124 	[DVBT_SYNC_LVL_PIP]	= {0x0b7,  2, 2},
125 	[DVBT_ERR_LVL_PIP]	= {0x0b7,  1, 1},
126 	[DVBT_VAL_LVL_PIP]	= {0x0b7,  0, 0},
127 	[DVBT_CKOUTPAR_PID]	= {0x0b9,  4, 4},
128 	[DVBT_CKOUT_PWR_PID]	= {0x0b9,  3, 3},
129 	[DVBT_SYNC_LVL_PID]	= {0x0b9,  2, 2},
130 	[DVBT_ERR_LVL_PID]	= {0x0b9,  1, 1},
131 	[DVBT_VAL_LVL_PID]	= {0x0b9,  0, 0},
132 	[DVBT_SM_PASS]		= {0x193, 11, 0},
133 	[DVBT_AD7_SETTING]	= {0x011, 15, 0},
134 	[DVBT_RSSI_R]		= {0x301,  6, 0},
135 	[DVBT_ACI_DET_IND]	= {0x312,  0, 0},
136 	[DVBT_REG_MON]		= {0x00d,  1, 0},
137 	[DVBT_REG_MONSEL]	= {0x00d,  2, 2},
138 	[DVBT_REG_GPE]		= {0x00d,  7, 7},
139 	[DVBT_REG_GPO]		= {0x010,  0, 0},
140 	[DVBT_REG_4MSEL]	= {0x013,  0, 0},
161 	reading_tmp = 0;  in rtl2832_rd_demod_reg()
162 	for (i = 0; i < len; i++)  in rtl2832_rd_demod_reg()
167 	return 0;  in rtl2832_rd_demod_reg()
191 	reading_tmp = 0;  in rtl2832_wr_demod_reg()
192 	for (i = 0; i < len; i++)  in rtl2832_wr_demod_reg()
198 	for (i = 0; i < len; i++)  in rtl2832_wr_demod_reg()
199 		writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;  in rtl2832_wr_demod_reg()
205 	return 0;  in rtl2832_wr_demod_reg()
217 	u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);  in rtl2832_set_if()
224 	pset_iffreq *= 0x400000;  in rtl2832_set_if()
227 	pset_iffreq = pset_iffreq & 0x3fffff;  in rtl2832_set_if()
239 	return 0;  in rtl2832_set_if()
254 		{DVBT_AD_EN_REG,		0x1},  in rtl2832_init()
255 		{DVBT_AD_EN_REG1,		0x1},  in rtl2832_init()
256 		{DVBT_RSD_BER_FAIL_VAL,		0x2800},  in rtl2832_init()
257 		{DVBT_MGD_THD0,			0x10},  in rtl2832_init()
258 		{DVBT_MGD_THD1,			0x20},  in rtl2832_init()
259 		{DVBT_MGD_THD2,			0x20},  in rtl2832_init()
260 		{DVBT_MGD_THD3,			0x40},  in rtl2832_init()
261 		{DVBT_MGD_THD4,			0x22},  in rtl2832_init()
262 		{DVBT_MGD_THD5,			0x32},  in rtl2832_init()
263 		{DVBT_MGD_THD6,			0x37},  in rtl2832_init()
264 		{DVBT_MGD_THD7,			0x39},  in rtl2832_init()
265 		{DVBT_EN_BK_TRK,		0x0},  in rtl2832_init()
266 		{DVBT_EN_CACQ_NOTCH,		0x0},  in rtl2832_init()
267 		{DVBT_AD_AV_REF,		0x2a},  in rtl2832_init()
268 		{DVBT_REG_PI,			0x6},  in rtl2832_init()
269 		{DVBT_PIP_ON,			0x0},  in rtl2832_init()
270 		{DVBT_CDIV_PH0,			0x8},  in rtl2832_init()
271 		{DVBT_CDIV_PH1,			0x8},  in rtl2832_init()
272 		{DVBT_SCALE1_B92,		0x4},  in rtl2832_init()
273 		{DVBT_SCALE1_B93,		0xb0},  in rtl2832_init()
274 		{DVBT_SCALE1_BA7,		0x78},  in rtl2832_init()
275 		{DVBT_SCALE1_BA9,		0x28},  in rtl2832_init()
276 		{DVBT_SCALE1_BAA,		0x59},  in rtl2832_init()
277 		{DVBT_SCALE1_BAB,		0x83},  in rtl2832_init()
278 		{DVBT_SCALE1_BAC,		0xd4},  in rtl2832_init()
279 		{DVBT_SCALE1_BB0,		0x65},  in rtl2832_init()
280 		{DVBT_SCALE1_BB1,		0x43},  in rtl2832_init()
281 		{DVBT_KB_P1,			0x1},  in rtl2832_init()
282 		{DVBT_KB_P2,			0x4},  in rtl2832_init()
283 		{DVBT_KB_P3,			0x7},  in rtl2832_init()
284 		{DVBT_K1_CR_STEP12,		0xa},  in rtl2832_init()
285 		{DVBT_REG_GPE,			0x1},  in rtl2832_init()
286 		{DVBT_SERIAL,			0x0},  in rtl2832_init()
287 		{DVBT_CDIV_PH0,			0x9},  in rtl2832_init()
288 		{DVBT_CDIV_PH1,			0x9},  in rtl2832_init()
289 		{DVBT_MPEG_IO_OPT_2_2,		0x0},  in rtl2832_init()
290 		{DVBT_MPEG_IO_OPT_1_0,		0x0},  in rtl2832_init()
291 		{DVBT_TRK_KS_P2,		0x4},  in rtl2832_init()
292 		{DVBT_TRK_KS_I2,		0x7},  in rtl2832_init()
293 		{DVBT_TR_THD_SET2,		0x6},  in rtl2832_init()
294 		{DVBT_TRK_KC_I2,		0x5},  in rtl2832_init()
295 		{DVBT_CR_THD_SET2,		0x1},  in rtl2832_init()
300 	ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);  in rtl2832_init()
304 	for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {  in rtl2832_init()
346 	for (i = 0; i < len; i++) {  in rtl2832_init()
354 	c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;  in rtl2832_init()
356 	c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;  in rtl2832_init()
358 	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;  in rtl2832_init()
360 	c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;  in rtl2832_init()
363 	return 0;  in rtl2832_init()
378 	dev->fe_status = 0;  in rtl2832_sleep()
380 	ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);  in rtl2832_sleep()
384 	return 0;  in rtl2832_sleep()
400 	return 0;  in rtl2832_get_tune_settings()
414 		0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,  in rtl2832_set_frontend()
415 		0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,  in rtl2832_set_frontend()
416 		0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,  in rtl2832_set_frontend()
417 		0x19, 0xe0,  in rtl2832_set_frontend()
422 		0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,  in rtl2832_set_frontend()
423 		0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,  in rtl2832_set_frontend()
424 		0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,  in rtl2832_set_frontend()
425 		0x19, 0x10,  in rtl2832_set_frontend()
430 		0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,  in rtl2832_set_frontend()
431 		0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,  in rtl2832_set_frontend()
432 		0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,  in rtl2832_set_frontend()
433 		0x19, 0xe0,  in rtl2832_set_frontend()
459 		i = 0;  in rtl2832_set_frontend()
477 	for (j = 0; j < sizeof(bw_params[0]); j++) {  in rtl2832_set_frontend()
479 					0x11c + j, &bw_params[i][j], 1);  in rtl2832_set_frontend()
489 	num *= 0x400000;  in rtl2832_set_frontend()
491 	resamp_ratio =  num & 0x3ffffff;  in rtl2832_set_frontend()
504 	cfreq_off_ratio = num & 0xfffff;  in rtl2832_set_frontend()
510 	ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);  in rtl2832_set_frontend()
514 	ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);  in rtl2832_set_frontend()
518 	return 0;  in rtl2832_set_frontend()
533 		return 0;  in rtl2832_get_frontend()
535 	ret = regmap_bulk_read(dev->regmap, 0x33c, buf, 2);  in rtl2832_get_frontend()
539 	ret = regmap_bulk_read(dev->regmap, 0x351, &buf[2], 1);  in rtl2832_get_frontend()
545 	switch ((buf[0] >> 2) & 3) {  in rtl2832_get_frontend()
546 	case 0:  in rtl2832_get_frontend()
558 	case 0:  in rtl2832_get_frontend()
565 	switch ((buf[2] >> 0) & 3) {  in rtl2832_get_frontend()
566 	case 0:  in rtl2832_get_frontend()
580 	switch ((buf[0] >> 4) & 7) {  in rtl2832_get_frontend()
581 	case 0:  in rtl2832_get_frontend()
596 	case 0:  in rtl2832_get_frontend()
613 	switch ((buf[1] >> 0) & 7) {  in rtl2832_get_frontend()
614 	case 0:  in rtl2832_get_frontend()
631 	return 0;  in rtl2832_get_frontend()
649 	*status = 0;  in rtl2832_read_status()
651 		return 0;  in rtl2832_read_status()
670 		ret = regmap_bulk_read(dev->regmap, 0x305, &u8tmp, 1);  in rtl2832_read_status()
677 		u16tmp = u8tmp << 8 | u8tmp << 0;  in rtl2832_read_status()
679 		c->strength.stat[0].scale = FE_SCALE_RELATIVE;  in rtl2832_read_status()
680 		c->strength.stat[0].uvalue = u16tmp;  in rtl2832_read_status()
682 		c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;  in rtl2832_read_status()
696 		ret = regmap_bulk_read(dev->regmap, 0x33c, &u8tmp, 1);  in rtl2832_read_status()
700 		constellation = (u8tmp >> 2) & 0x03; /* [3:2] */  in rtl2832_read_status()
705 		hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */  in rtl2832_read_status()
709 		ret = regmap_bulk_read(dev->regmap, 0x40c, buf, 2);  in rtl2832_read_status()
713 		u16tmp = buf[0] << 8 | buf[1] << 0;  in rtl2832_read_status()
718 			tmp = 0;  in rtl2832_read_status()
722 		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;  in rtl2832_read_status()
723 		c->cnr.stat[0].svalue = tmp;  in rtl2832_read_status()
725 		c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;  in rtl2832_read_status()
730 		ret = regmap_bulk_read(dev->regmap, 0x34e, buf, 2);  in rtl2832_read_status()
734 		u16tmp = buf[0] << 8 | buf[1] << 0;  in rtl2832_read_status()
740 		c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;  in rtl2832_read_status()
741 		c->post_bit_error.stat[0].uvalue = dev->post_bit_error;  in rtl2832_read_status()
742 		c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;  in rtl2832_read_status()
743 		c->post_bit_count.stat[0].uvalue = dev->post_bit_count;  in rtl2832_read_status()
745 		c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;  in rtl2832_read_status()
746 		c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;  in rtl2832_read_status()
749 	return 0;  in rtl2832_read_status()
760 	if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)  in rtl2832_read_snr()
761 		*snr = div_s64(c->cnr.stat[0].svalue, 100);  in rtl2832_read_snr()
763 		*snr = 0;  in rtl2832_read_snr()
765 	return 0;  in rtl2832_read_snr()
775 	return 0;  in rtl2832_read_ber()
791 	ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x00);  in rtl2832_i2c_gate_work()
810 	ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);  in rtl2832_select()
814 	return 0;  in rtl2832_select()
825 	return 0;  in rtl2832_deselect()
868 	case 0x305:  in rtl2832_volatile_reg()
869 	case 0x33c:  in rtl2832_volatile_reg()
870 	case 0x34e:  in rtl2832_volatile_reg()
871 	case 0x351:  in rtl2832_volatile_reg()
872 	case 0x40c ... 0x40d:  in rtl2832_volatile_reg()
894 	return dev->muxc->adapter[0];  in rtl2832_get_i2c_adapter()
905 		ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);  in rtl2832_slave_ts_ctrl()
908 		ret = regmap_bulk_write(dev->regmap, 0x10c, "\x5f\xff", 2);  in rtl2832_slave_ts_ctrl()
911 		ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);  in rtl2832_slave_ts_ctrl()
914 		ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x18", 1);  in rtl2832_slave_ts_ctrl()
917 		ret = regmap_bulk_write(dev->regmap, 0x192, "\x7f\xf7\xff", 3);  in rtl2832_slave_ts_ctrl()
921 		ret = regmap_bulk_write(dev->regmap, 0x192, "\x00\x0f\xff", 3);  in rtl2832_slave_ts_ctrl()
924 		ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x08", 1);  in rtl2832_slave_ts_ctrl()
927 		ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x0);  in rtl2832_slave_ts_ctrl()
930 		ret = regmap_bulk_write(dev->regmap, 0x10c, "\x00\x00", 2);  in rtl2832_slave_ts_ctrl()
933 		ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);  in rtl2832_slave_ts_ctrl()
940 	return 0;  in rtl2832_slave_ts_ctrl()
957 		u8tmp = 0x80;  in rtl2832_pid_filter_ctrl()
959 		u8tmp = 0x00;  in rtl2832_pid_filter_ctrl()
962 		ret = regmap_update_bits(dev->regmap, 0x021, 0xc0, u8tmp);  in rtl2832_pid_filter_ctrl()
964 		ret = regmap_update_bits(dev->regmap, 0x061, 0xc0, u8tmp);  in rtl2832_pid_filter_ctrl()
968 	return 0;  in rtl2832_pid_filter_ctrl()
985 	/* skip invalid PIDs (0x2000) */  in rtl2832_pid_filter()
986 	if (pid > 0x1fff || index >= 32)  in rtl2832_pid_filter()
987 		return 0;  in rtl2832_pid_filter()
995 	buf[0] = (dev->filters >>  0) & 0xff;  in rtl2832_pid_filter()
996 	buf[1] = (dev->filters >>  8) & 0xff;  in rtl2832_pid_filter()
997 	buf[2] = (dev->filters >> 16) & 0xff;  in rtl2832_pid_filter()
998 	buf[3] = (dev->filters >> 24) & 0xff;  in rtl2832_pid_filter()
1001 		ret = regmap_bulk_write(dev->regmap, 0x022, buf, 4);  in rtl2832_pid_filter()
1003 		ret = regmap_bulk_write(dev->regmap, 0x062, buf, 4);  in rtl2832_pid_filter()
1008 	buf[0] = (pid >> 8) & 0xff;  in rtl2832_pid_filter()
1009 	buf[1] = (pid >> 0) & 0xff;  in rtl2832_pid_filter()
1012 		ret = regmap_bulk_write(dev->regmap, 0x026 + 2 * index, buf, 2);  in rtl2832_pid_filter()
1014 		ret = regmap_bulk_write(dev->regmap, 0x066 + 2 * index, buf, 2);  in rtl2832_pid_filter()
1018 	return 0;  in rtl2832_pid_filter()
1033 			.selector_reg     = 0x00,  in rtl2832_probe()
1034 			.selector_mask    = 0xff,  in rtl2832_probe()
1035 			.selector_shift   = 0,  in rtl2832_probe()
1036 			.window_start     = 0,  in rtl2832_probe()
1037 			.window_len       = 0x100,  in rtl2832_probe()
1038 			.range_min        = 0 * 0x100,  in rtl2832_probe()
1039 			.range_max        = 5 * 0x100,  in rtl2832_probe()
1062 	dev->regmap_config.max_register = 5 * 0x100;  in rtl2832_probe()
1073 	ret = regmap_bulk_read(dev->regmap, 0x000, &tmp, 1);  in rtl2832_probe()
1078 	dev->muxc = i2c_mux_alloc(i2c, &i2c->dev, 1, 0, I2C_MUX_LOCKED,  in rtl2832_probe()
1085 	ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);  in rtl2832_probe()
1102 	return 0;  in rtl2832_probe()
1128 	{"rtl2832", 0},