43 #define HELENE_AUTO		0xff
44 #define HELENE_OFFSET(ofs)	((u8)(ofs) & 0x1F)
45 #define HELENE_BW_6		0x00
46 #define HELENE_BW_7		0x01
47 #define HELENE_BW_8		0x02
48 #define HELENE_BW_1_7		0x03
133 	/* < Addr:0x69 Bit[6:4] : RFVGA gain.
134 	 * 0xFF means Auto. (RF_GAIN_SEL = 1)
137 	/* < Addr:0x69 Bit[3:0] : IF_BPF gain.
140 	/* < Addr:0x6B Bit[3:0] : RF overload
144 	/* < Addr:0x6B Bit[3:0] : RF overload
148 	/* < Addr:0x6B Bit[3:0] : RF overload
152 	/* < Addr:0x6C Bit[2:0] :
156 	/* < Addr:0x6C Bit[2:0] :
160 	/* < Addr:0x6C Bit[2:0] :
164 	/* < Addr:0x6D Bit[5:4] :
168 	/* < Addr:0x6D Bit[1:0] :
169 	 * 6MHzBW(0x00) or 7MHzBW(0x01)
170 	 * or 8MHzBW(0x02) or 1.7MHzBW(0x03)
173 	/* < Addr:0x6E Bit[4:0] :
177 	/* < Addr:0x6F Bit[4:0] :
182 	/* < Addr:0x9C Bit[0]   :
183 	 * Local polarity. (0: Upper Local, 1: Lower Local)
191 	{HELENE_AUTO, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 		HELENE_BW_6, HELENE_OFFSET(0),  HELENE_OFFSET(0),  0x00},
195 	{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
196 		HELENE_BW_6,  HELENE_OFFSET(0),  HELENE_OFFSET(1),  0x00},
198 	{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
199 		HELENE_BW_6,  HELENE_OFFSET(0),  HELENE_OFFSET(1),  0x00},
200 	{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
201 		HELENE_BW_6,  HELENE_OFFSET(3),  HELENE_OFFSET(1),  0x00},
203 	{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
204 		HELENE_BW_7,  HELENE_OFFSET(11), HELENE_OFFSET(5),  0x00},
206 	{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
207 		HELENE_BW_8,  HELENE_OFFSET(2),  HELENE_OFFSET(-3), 0x00},
209 	{HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
210 		HELENE_BW_8,  HELENE_OFFSET(2),  HELENE_OFFSET(-3), 0x00},
212 	{HELENE_AUTO, 0x03, 0x04, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x00,
213 		HELENE_BW_8,  HELENE_OFFSET(2),  HELENE_OFFSET(-3), 0x00},
215 	{HELENE_AUTO, 0x03, 0x04, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x00,
216 		HELENE_BW_8,  HELENE_OFFSET(-1), HELENE_OFFSET(4),  0x00},
219 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x03, 0x03, 0x03, 0x00,
220 		HELENE_BW_6,  HELENE_OFFSET(-6), HELENE_OFFSET(-3), 0x00},
222 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
223 		HELENE_BW_6,  HELENE_OFFSET(-6), HELENE_OFFSET(-3), 0x00},
225 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
226 		HELENE_BW_6,  HELENE_OFFSET(-9), HELENE_OFFSET(-5), 0x00},
228 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
229 		HELENE_BW_7,  HELENE_OFFSET(-7), HELENE_OFFSET(-6), 0x00},
231 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
232 		HELENE_BW_8,  HELENE_OFFSET(-5), HELENE_OFFSET(-7), 0x00},
234 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
235 		HELENE_BW_6,  HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
237 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
238 		HELENE_BW_6,  HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
240 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
241 		HELENE_BW_7,  HELENE_OFFSET(-6), HELENE_OFFSET(-5), 0x00},
243 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
244 		HELENE_BW_8,  HELENE_OFFSET(-4), HELENE_OFFSET(-6), 0x00},
246 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
247 		HELENE_BW_1_7, HELENE_OFFSET(-10), HELENE_OFFSET(-10), 0x00},
249 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
250 		HELENE_BW_6,  HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
252 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
253 		HELENE_BW_6,  HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
255 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
256 		HELENE_BW_7,  HELENE_OFFSET(-6), HELENE_OFFSET(-5), 0x00},
258 	{HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
259 		HELENE_BW_8,  HELENE_OFFSET(-4), HELENE_OFFSET(-6), 0x00},
261 	{HELENE_AUTO, 0x05, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x00,
262 		HELENE_BW_6,  HELENE_OFFSET(-6), HELENE_OFFSET(-4), 0x00},
264 	{HELENE_AUTO, 0x05, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x00,
265 		HELENE_BW_8,  HELENE_OFFSET(-2), HELENE_OFFSET(-3), 0x00},
267 	{HELENE_AUTO, 0x03, 0x09, 0x09, 0x09, 0x02, 0x02, 0x02, 0x00,
268 		HELENE_BW_6,  HELENE_OFFSET(-6), HELENE_OFFSET(-2), 0x00},
270 	{HELENE_AUTO, 0x03, 0x09, 0x09, 0x09, 0x02, 0x02, 0x02, 0x00,
271 		HELENE_BW_8,  HELENE_OFFSET(-2), HELENE_OFFSET(0),  0x00},
273 	{HELENE_AUTO, 0x04, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
274 		HELENE_BW_8,  HELENE_OFFSET(2),  HELENE_OFFSET(1),  0x00}
281 	dev_dbg(&priv->i2c->dev, "helene: I2C %s reg 0x%02x size %d\n",  in helene_i2c_debug()
282 			(write == 0 ? "read" : "write"), reg, len);  in helene_i2c_debug()
295 			.flags = 0,  in helene_write_regs()
309 	buf[0] = reg;  in helene_write_regs()
312 	if (ret >= 0 && ret != 1)  in helene_write_regs()
314 	if (ret < 0) {  in helene_write_regs()
320 	return 0;  in helene_write_regs()
337 			.flags = 0,  in helene_read_regs()
348 	ret = i2c_transfer(priv->i2c, &msg[0], 1);  in helene_read_regs()
349 	if (ret >= 0 && ret != 1)  in helene_read_regs()
351 	if (ret < 0) {  in helene_read_regs()
358 	if (ret >= 0 && ret != 1)  in helene_read_regs()
360 	if (ret < 0) {  in helene_read_regs()
366 	helene_i2c_debug(priv, reg, 0, val, len);  in helene_read_regs()
367 	return 0;  in helene_read_regs()
381 	if (mask != 0xff) {  in helene_set_reg_bits()
383 		if (res != 0)  in helene_set_reg_bits()
385 		data = ((data & mask) | (rdata & (mask ^ 0xFF)));  in helene_set_reg_bits()
394 		return 0;  in helene_enter_power_save()
397 	helene_write_reg(priv, 0x88, 0x0);  in helene_enter_power_save()
400 	helene_write_reg(priv, 0x87, 0xC0);  in helene_enter_power_save()
403 	return 0;  in helene_enter_power_save()
410 		return 0;  in helene_leave_power_save()
413 	helene_write_reg(priv, 0x87, 0xC4);  in helene_leave_power_save()
416 	helene_write_reg(priv, 0x88, 0x40);  in helene_leave_power_save()
419 	return 0;  in helene_leave_power_save()
445 	return 0;  in helene_sleep()
518 	uint32_t frequency4kHz = 0;  in helene_set_params_s()
532 		priv->set_tuner(priv->set_tuner_data, 0);  in helene_set_params_s()
536 	helene_write_reg(priv, 0x15, 0x02);  in helene_set_params_s()
539 	helene_write_reg(priv, 0x43, 0x06);  in helene_set_params_s()
541 	/* Analog block setting (0x6A, 0x6B) */  in helene_set_params_s()
542 	data[0] = 0x00;  in helene_set_params_s()
543 	data[1] = 0x00;  in helene_set_params_s()
544 	helene_write_regs(priv, 0x6A, data, 2);  in helene_set_params_s()
545 	helene_write_reg(priv, 0x75, 0x99);  in helene_set_params_s()
546 	helene_write_reg(priv, 0x9D, 0x00);  in helene_set_params_s()
548 	/* Tuning setting for CPU (0x61) */  in helene_set_params_s()
549 	helene_write_reg(priv, 0x61, 0x07);  in helene_set_params_s()
551 	/* Satellite mode select (0x01) */  in helene_set_params_s()
552 	helene_write_reg(priv, 0x01, 0x01);  in helene_set_params_s()
554 	/* Clock enable for internal logic block, CPU wake-up (0x04, 0x05) */  in helene_set_params_s()
555 	data[0] = 0xC4;  in helene_set_params_s()
556 	data[1] = 0x40;  in helene_set_params_s()
560 		data[2] = 0x02;  in helene_set_params_s()
563 		data[2] = 0x02;  in helene_set_params_s()
566 		data[2] = 0x03;  in helene_set_params_s()
569 		data[2] = 0x05;  in helene_set_params_s()
577 	/* Setting for analog block (0x07). LOOPFILTER INTERNAL */  in helene_set_params_s()
578 	data[3] = 0x80;  in helene_set_params_s()
581 	 * (0x08, 0x09, 0x0A, 0x0B). LOOPFILTER INTERNAL  in helene_set_params_s()
584 		data[4] = 0x58;  in helene_set_params_s()
586 		data[4] = 0x70;  in helene_set_params_s()
588 	data[5] = 0x1E;  in helene_set_params_s()
589 	data[6] = 0x02;  in helene_set_params_s()
590 	data[7] = 0x24;  in helene_set_params_s()
592 	/* Enable for analog block (0x0C, 0x0D, 0x0E). SAT LNA ON */  in helene_set_params_s()
593 	data[8] = 0x0F;  in helene_set_params_s()
594 	data[8] |= 0xE0; /* POWERSAVE_TERR_RF_ACTIVE */  in helene_set_params_s()
595 	data[9]  = 0x02;  in helene_set_params_s()
596 	data[10] = 0x1E;  in helene_set_params_s()
598 	/* Setting for LPF cutoff frequency (0x0F) */  in helene_set_params_s()
601 		data[11] = 0x22; /* 22MHz */  in helene_set_params_s()
605 			data[11] = 0x05;  in helene_set_params_s()
618 			data[11] = 0x05;  in helene_set_params_s()
635 	/* RF tuning frequency setting (0x10, 0x11, 0x12) */  in helene_set_params_s()
637 	data[12] = (uint8_t)(frequency4kHz & 0xFF);         /* FRF_L */  in helene_set_params_s()
638 	data[13] = (uint8_t)((frequency4kHz >> 8) & 0xFF);  /* FRF_M */  in helene_set_params_s()
639 	/* FRF_H (bit[3:0]) */  in helene_set_params_s()
640 	data[14] = (uint8_t)((frequency4kHz >> 16) & 0x0F);  in helene_set_params_s()
642 	/* Tuning command (0x13) */  in helene_set_params_s()
643 	data[15] = 0xFF;  in helene_set_params_s()
645 	/* Setting for IQOUT_LIMIT (0x14) 0.75Vpp */  in helene_set_params_s()
646 	data[16] = 0x00;  in helene_set_params_s()
648 	/* Enable IQ output (0x15) */  in helene_set_params_s()
649 	data[17] = 0x01;  in helene_set_params_s()
651 	helene_write_regs(priv, 0x04, data, 18);  in helene_set_params_s()
657 	return 0;  in helene_set_params_s()
683 	helene_write_reg(priv, 0x01, 0x00);  in helene_set_params_t()
686 	helene_write_reg(priv, 0x74, 0x02);  in helene_set_params_t()
691 	/* Initial setting for internal analog block (0x91, 0x92) */  in helene_set_params_t()
694 		data[0] = 0x16;  in helene_set_params_t()
695 		data[1] = 0x26;  in helene_set_params_t()
697 		data[0] = 0x10;  in helene_set_params_t()
698 		data[1] = 0x20;  in helene_set_params_t()
700 	helene_write_regs(priv, 0x91, data, 2);  in helene_set_params_t()
704 		data[0] = 0x90;  in helene_set_params_t()
706 		data[0] = 0x00;  in helene_set_params_t()
708 	/* Setting for local polarity (0x9D) */  in helene_set_params_t()
709 	data[1] = (uint8_t)(terr_params[tv_system].IS_LOWERLOCAL & 0x01);  in helene_set_params_t()
710 	helene_write_regs(priv, 0x9C, data, 2);  in helene_set_params_t()
713 	data[0] = 0xEE;  in helene_set_params_t()
714 	data[1] = 0x02;  in helene_set_params_t()
715 	data[2] = 0x1E;  in helene_set_params_t()
716 	data[3] = 0x67; /* Tuning setting for CPU */  in helene_set_params_t()
721 		data[4] = 0x18;  in helene_set_params_t()
723 		data[4] = 0x03;  in helene_set_params_t()
727 		data[5] = 0x38;  in helene_set_params_t()
728 		data[6] = 0x1E;  in helene_set_params_t()
729 		data[7] = 0x02;  in helene_set_params_t()
730 		data[8] = 0x24;  in helene_set_params_t()
733 		data[5] = 0x1C;  in helene_set_params_t()
734 		data[6] = 0x78;  in helene_set_params_t()
735 		data[7] = 0x08;  in helene_set_params_t()
736 		data[8] = 0x1C;  in helene_set_params_t()
738 		data[5] = 0xB4;  in helene_set_params_t()
739 		data[6] = 0x78;  in helene_set_params_t()
740 		data[7] = 0x08;  in helene_set_params_t()
741 		data[8] = 0x30;  in helene_set_params_t()
743 	helene_write_regs(priv, 0x5E, data, 9);  in helene_set_params_t()
745 	/* LT_AMP_EN should be 0 */  in helene_set_params_t()
746 	helene_set_reg_bits(priv, 0x67, 0x0, 0x02);  in helene_set_params_t()
749 	data[0] = 0x00; /* 1.5Vpp */  in helene_set_params_t()
753 		data[1] = 0x80; /* RF_GAIN_SEL = 1 */  in helene_set_params_t()
756 					<< 4) & 0x70);  in helene_set_params_t()
759 	data[1] |= (uint8_t)(terr_params[tv_system].IF_BPF_GC & 0x0F);  in helene_set_params_t()
761 	/* Setting for internal RFAGC (0x6A, 0x6B, 0x6C) */  in helene_set_params_t()
762 	data[2] = 0x00;  in helene_set_params_t()
765 				& 0x0F);  in helene_set_params_t()
767 				& 0x07);  in helene_set_params_t()
770 				& 0x0F);  in helene_set_params_t()
772 				& 0x07);  in helene_set_params_t()
775 				& 0x0F);  in helene_set_params_t()
777 				& 0x07);  in helene_set_params_t()
779 	data[4] |= 0x20;  in helene_set_params_t()
783 	/* IF filter center frequency offset (IF_BPF_F0) (0x6D) */  in helene_set_params_t()
784 	data[5] = (uint8_t)((terr_params[tv_system].IF_BPF_F0 << 4) & 0x30);  in helene_set_params_t()
786 	/* IF filter band width (BW) (0x6D) */  in helene_set_params_t()
787 	data[5] |= (uint8_t)(terr_params[tv_system].BW & 0x03);  in helene_set_params_t()
789 	/* IF frequency offset value (FIF_OFFSET) (0x6E) */  in helene_set_params_t()
790 	data[6] = (uint8_t)(terr_params[tv_system].FIF_OFFSET & 0x1F);  in helene_set_params_t()
792 	/* IF band width offset value (BW_OFFSET) (0x6F) */  in helene_set_params_t()
793 	data[7] = (uint8_t)(terr_params[tv_system].BW_OFFSET & 0x1F);  in helene_set_params_t()
795 	/* RF tuning frequency setting (0x70, 0x71, 0x72) */  in helene_set_params_t()
796 	data[8]  = (uint8_t)(frequencykHz & 0xFF);         /* FRF_L */  in helene_set_params_t()
797 	data[9]  = (uint8_t)((frequencykHz >> 8) & 0xFF);  /* FRF_M */  in helene_set_params_t()
799 			& 0x0F); /* FRF_H (bit[3:0]) */  in helene_set_params_t()
802 	data[11] = 0xFF;  in helene_set_params_t()
804 	/* Enable IF output, AGC and IFOUT pin selection (0x74) */  in helene_set_params_t()
805 	data[12] = 0x01;  in helene_set_params_t()
809 		data[13] = 0xD9;  in helene_set_params_t()
810 		data[14] = 0x0F;  in helene_set_params_t()
811 		data[15] = 0x24;  in helene_set_params_t()
812 		data[16] = 0x87;  in helene_set_params_t()
814 		data[13] = 0x99;  in helene_set_params_t()
815 		data[14] = 0x00;  in helene_set_params_t()
816 		data[15] = 0x24;  in helene_set_params_t()
817 		data[16] = 0x87;  in helene_set_params_t()
820 	helene_write_regs(priv, 0x68, data, 17);  in helene_set_params_t()
826 	return 0;  in helene_set_params_t()
847 	return 0;  in helene_get_frequency()
899 	u8 dataT[] = { 0x06, 0x00, 0x02, 0x00 };  in helene_x_pon()
901 	u8 dataS[] = { 0x05, 0x06 };  in helene_x_pon()
902 	u8 cdata[] = {0x7A, 0x01};  in helene_x_pon()
907 	helene_write_reg(priv, 0x01, 0x00);  in helene_x_pon()
909 	helene_write_reg(priv, 0x67, dataT[3]);  in helene_x_pon()
910 	helene_write_reg(priv, 0x43, dataS[1]);  in helene_x_pon()
911 	helene_write_regs(priv, 0x5E, dataT, 3);  in helene_x_pon()
912 	helene_write_reg(priv, 0x0C, dataS[0]);  in helene_x_pon()
915 	helene_write_regs(priv, 0x99, cdata, sizeof(cdata));  in helene_x_pon()
917 	/* 0x81 - 0x94 */  in helene_x_pon()
919 		data[0] = 0x10; /* xtal 16 MHz */  in helene_x_pon()
921 		data[0] = 0x18; /* xtal 24 MHz */  in helene_x_pon()
922 	data[1] = (uint8_t)(0x80 | (0x04 & 0x1F)); /* 4 x 25 = 100uA */  in helene_x_pon()
923 	data[2] = (uint8_t)(0x80 | (0x26 & 0x7F)); /* 38 x 0.25 = 9.5pF */  in helene_x_pon()
924 	data[3] = 0x80; /* REFOUT signal output 500mVpp */  in helene_x_pon()
925 	data[4] = 0x00; /* GPIO settings */  in helene_x_pon()
926 	data[5] = 0x00; /* GPIO settings */  in helene_x_pon()
927 	data[6] = 0xC4; /* Clock enable for internal logic block */  in helene_x_pon()
928 	data[7] = 0x40; /* Start CPU boot-up */  in helene_x_pon()
929 	data[8] = 0x10; /* For burst-write */  in helene_x_pon()
932 	data[9] = 0x00;  in helene_x_pon()
933 	data[10] = 0x45;  in helene_x_pon()
934 	data[11] = 0x75;  in helene_x_pon()
936 	data[12] = 0x07; /* Setting for analog block */  in helene_x_pon()
939 	data[13] = 0x1C;  in helene_x_pon()
940 	data[14] = 0x3F;  in helene_x_pon()
941 	data[15] = 0x02;  in helene_x_pon()
942 	data[16] = 0x10;  in helene_x_pon()
943 	data[17] = 0x20;  in helene_x_pon()
944 	data[18] = 0x0A;  in helene_x_pon()
945 	data[19] = 0x00;  in helene_x_pon()
947 	helene_write_regs(priv, 0x81, data, sizeof(data));  in helene_x_pon()
950 	helene_write_reg(priv, 0x9B, 0x00);  in helene_x_pon()
955 	helene_read_regs(priv, 0x1A, rdata, sizeof(rdata));  in helene_x_pon()
957 	if (rdata[0] != 0x00) {  in helene_x_pon()
959 				"HELENE tuner CPU error 0x%x\n", rdata[0]);  in helene_x_pon()
964 	cdata[0] = 0x90;  in helene_x_pon()
965 	cdata[1] = 0x06;  in helene_x_pon()
966 	helene_write_regs(priv, 0x17, cdata, sizeof(cdata));  in helene_x_pon()
968 	helene_read_reg(priv, 0x19, data);  in helene_x_pon()
969 	helene_write_reg(priv, 0x95, (uint8_t)((data[0] >> 4) & 0x0F));  in helene_x_pon()
972 	helene_write_reg(priv, 0x74, 0x02);  in helene_x_pon()
975 	helene_write_reg(priv, 0x88, 0x00);  in helene_x_pon()
978 	helene_write_reg(priv, 0x87, 0xC0);  in helene_x_pon()
981 	helene_write_reg(priv, 0x80, 0x01);  in helene_x_pon()
984 	cdata[0] = 0x07;  in helene_x_pon()
985 	cdata[1] = 0x00;  in helene_x_pon()
986 	helene_write_regs(priv, 0x41, cdata, sizeof(cdata));  in helene_x_pon()
991 	return 0;  in helene_x_pon()
1012 	if (helene_x_pon(priv) != 0) {  in helene_attach_s()
1018 		fe->ops.i2c_gate_ctrl(fe, 0);  in helene_attach_s()
1048 	if (helene_x_pon(priv) != 0) {  in helene_attach()
1054 		fe->ops.i2c_gate_ctrl(fe, 0);  in helene_attach()
1086 	if (helene_x_pon(priv) != 0)  in helene_probe()
1090 		fe->ops.i2c_gate_ctrl(fe, 0);  in helene_probe()
1100 	return 0;  in helene_probe()