Lines Matching +full:0 +full:x52
17 #define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
18 #define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
21 #define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
26 #define END_OF_TABLE 0xFF, 0xFF, 0xFF, 0xFF
35 0x26, 0x00, /* 0 -> ring.rdy; */
36 0x60, 0x04, /* r0rami.dt -> ring.xba; */
37 0x61, 0x04, /* r0rami.dt -> ring.xad; */
38 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
39 0x40, 0x00, /* (long immediate) */
40 0x64, 0x04, /* r0rami.dt -> ring.len; */
41 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
42 0x26, 0x00, /* 0 -> ring.rdy; */
43 0x38, 0x00, /* 0 -> jumps.ad; */
56 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
57 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
58 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
59 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
60 0x23, 0x00, /* &data -> ring.iad; */
61 0x24, 0x00, /* 0 -> ring.len; */
62 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
63 0x26, 0x00, /* 0 -> ring.rdy; */
64 0x42, 0x00, /* &data+1 -> w0ram.ad; */
65 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
66 0x63, 0x00, /* &data+1 -> ring.iad; */
67 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
68 0x26, 0x00, /* 0 -> ring.rdy; */
69 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
70 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
71 0x26, 0x00, /* 0 -> ring.rdy; */
72 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
73 0x23, 0x00, /* &data -> ring.iad; */
74 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
75 0x26, 0x00, /* 0 -> ring.rdy; */
76 0x42, 0x00, /* &data+1 -> w0ram.ad; */
77 0x0F, 0x04, /* r0ram.dt -> and.op; */
78 0x1C, 0x06, /* reg0.dt -> and.tr; */
79 0xCF, 0x04, /* and.rs -> add.op; */
80 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
81 0xD0, 0x04, /* add.rs -> add.tr; */
82 0xC8, 0x04, /* add.rs -> reg0.dt; */
83 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
84 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
85 0x01, 0x00, /* 0 -> w0rami.dt; */
86 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
87 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
88 0x01, 0x00, /* 0 -> w0rami.dt; */
89 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
90 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
91 0x01, 0x00, /* 0 -> w0rami.dt; */
92 0x01, 0x00, /* 0 -> w0rami.dt; */
93 0x01, 0x00, /* 0 -> w0rami.dt; */
94 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
95 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
96 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
97 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
98 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
100 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
101 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
103 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
105 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
107 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
110 WR16(B_HI_CT_REG_COMM_STATE__A, 0),
117 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
118 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
119 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
120 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
121 0x23, 0x00, /* &data -> ring.iad; */
122 0x24, 0x00, /* 0 -> ring.len; */
123 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
124 0x26, 0x00, /* 0 -> ring.rdy; */
125 0x42, 0x00, /* &data+1 -> w0ram.ad; */
126 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
127 0x63, 0x00, /* &data+1 -> ring.iad; */
128 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
129 0x26, 0x00, /* 0 -> ring.rdy; */
130 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
131 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
132 0x26, 0x00, /* 0 -> ring.rdy; */
133 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
134 0x23, 0x00, /* &data -> ring.iad; */
135 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
136 0x26, 0x00, /* 0 -> ring.rdy; */
137 0x42, 0x00, /* &data+1 -> w0ram.ad; */
138 0x0F, 0x04, /* r0ram.dt -> and.op; */
139 0x1C, 0x06, /* reg0.dt -> and.tr; */
140 0xCF, 0x04, /* and.rs -> add.op; */
141 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
142 0xD0, 0x04, /* add.rs -> add.tr; */
143 0xC8, 0x04, /* add.rs -> reg0.dt; */
144 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
145 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
146 0x01, 0x00, /* 0 -> w0rami.dt; */
147 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
148 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
149 0x01, 0x00, /* 0 -> w0rami.dt; */
150 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
151 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
152 0x01, 0x00, /* 0 -> w0rami.dt; */
153 0x01, 0x00, /* 0 -> w0rami.dt; */
154 0x01, 0x00, /* 0 -> w0rami.dt; */
155 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
156 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
157 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
158 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
159 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
161 WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
162 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
164 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
166 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
168 (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
171 WR16(B_HI_CT_REG_COMM_STATE__A, 0),
177 0x52, 0x00, /* CE_REG_FR_TREAL00__A */
178 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
179 0x52, 0x00, /* CE_REG_FR_TREAL01__A */
180 0x00, 0x00, /* CE_REG_FR_TIMAG01__A */
181 0x52, 0x00, /* CE_REG_FR_TREAL02__A */
182 0x00, 0x00, /* CE_REG_FR_TIMAG02__A */
183 0x52, 0x00, /* CE_REG_FR_TREAL03__A */
184 0x00, 0x00, /* CE_REG_FR_TIMAG03__A */
185 0x52, 0x00, /* CE_REG_FR_TREAL04__A */
186 0x00, 0x00, /* CE_REG_FR_TIMAG04__A */
187 0x52, 0x00, /* CE_REG_FR_TREAL05__A */
188 0x00, 0x00, /* CE_REG_FR_TIMAG05__A */
189 0x52, 0x00, /* CE_REG_FR_TREAL06__A */
190 0x00, 0x00, /* CE_REG_FR_TIMAG06__A */
191 0x52, 0x00, /* CE_REG_FR_TREAL07__A */
192 0x00, 0x00, /* CE_REG_FR_TIMAG07__A */
193 0x52, 0x00, /* CE_REG_FR_TREAL08__A */
194 0x00, 0x00, /* CE_REG_FR_TIMAG08__A */
195 0x52, 0x00, /* CE_REG_FR_TREAL09__A */
196 0x00, 0x00, /* CE_REG_FR_TIMAG09__A */
197 0x52, 0x00, /* CE_REG_FR_TREAL10__A */
198 0x00, 0x00, /* CE_REG_FR_TIMAG10__A */
199 0x52, 0x00, /* CE_REG_FR_TREAL11__A */
200 0x00, 0x00, /* CE_REG_FR_TIMAG11__A */
202 0x52, 0x00, /* CE_REG_FR_MID_TAP__A */
204 0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */
205 0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */
206 0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */
207 0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */
208 0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */
209 0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */
210 0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */
211 0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */
212 0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */
213 0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */
214 0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */
215 0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */
216 0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */
218 0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */
219 0x90, 0x01, /* CE_REG_FR_RIO_G01__A */
220 0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */
221 0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */
222 0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */
223 0x85, 0x00, /* CE_REG_FR_RIO_G05__A */
224 0x72, 0x00, /* CE_REG_FR_RIO_G06__A */
225 0x64, 0x00, /* CE_REG_FR_RIO_G07__A */
226 0x59, 0x00, /* CE_REG_FR_RIO_G08__A */
227 0x50, 0x00, /* CE_REG_FR_RIO_G09__A */
228 0x49, 0x00, /* CE_REG_FR_RIO_G10__A */
230 0x10, 0x00, /* CE_REG_FR_MODE__A */
231 0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */
232 0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */
233 0x00, 0x02, /* CE_REG_FR_BYPASS__A */
234 0x0D, 0x00, /* CE_REG_FR_PM_SET__A */
235 0x07, 0x00, /* CE_REG_FR_ERR_SH__A */
236 0x04, 0x00, /* CE_REG_FR_MAN_SH__A */
237 0x06, 0x00, /* CE_REG_FR_TAP_SH__A */
244 0x00, 0x00, /* FE_AD_REG_PD__A */
245 0x01, 0x00, /* FE_AD_REG_INVEXT__A */
246 0x00, 0x00, /* FE_AD_REG_CLKNEG__A */
249 0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
250 0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
253 0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
254 0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
257 0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
258 0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
259 0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
260 0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */
261 0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
264 0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
265 0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
268 0x00, 0x00, /* FE_AG_REG_IND_WIN__A */
269 0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */
270 0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */
271 0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */
272 0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */
273 0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
274 0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
275 0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
276 0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
277 0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */
278 0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
279 0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
280 0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
281 0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
282 0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
283 0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
284 0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */
285 0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
286 0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
287 0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
288 0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
289 0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */
290 0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
291 0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
292 0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */
293 0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */
294 0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
295 0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
296 0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
299 0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
300 0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
303 0x05, 0x00, /* FE_FD_REG_SCL__A */
304 0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */
305 0x05, 0x00, /* FE_FD_REG_NR__A */
308 0x16, 0x00, /* FE_CF_REG_SCL__A */
309 0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */
310 0x06, 0x00, /* FE_CF_REG_NR__A */
311 0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */
312 0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */
315 0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */
316 0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */
322 /* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */
324 /* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */
325 /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
326 /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
329 WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
332 WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
334 WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
335 WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
336 WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
337 WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
338 WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
339 WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
340 WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
341 WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
347 WR16(B_FE_AD_REG_PD__A, 0x0000),
348 WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
349 WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
350 WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
351 WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
353 WR16(B_FE_AG_REG_IND_WIN__A, 0),
362 /* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
365 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
366 …/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005…
367 /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
370 WR16(B_FE_COMM_EXEC__A, 0x0001),
373 WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
374 WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
375 WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
376 WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
377 WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
378 WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
379 WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
380 WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
381 WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
382 WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
383 WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
385 WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
393 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
394 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
397 0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */
398 0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */
399 0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */
400 0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */
403 0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */
404 0x62, 0x00, /* CP_REG_AC_AVER_POW__A */
405 0x82, 0x00, /* CP_REG_AC_MAX_POW__A */
406 0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */
407 0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */
410 0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */
411 0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */
413 WR16(CP_REG_INTERVAL__A, 0x0005),
414 WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
415 WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
417 WR16(CP_REG_COMM_EXEC__A, 0x0001),
422 WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
423 WR16(B_CP_COMM_EXEC__A, 0x0001),
429 0x62, 0x00, /* CE_REG_AVG_POW__A */
430 0x78, 0x00, /* CE_REG_MAX_POW__A */
431 0x62, 0x00, /* CE_REG_ATT__A */
432 0x17, 0x00, /* CE_REG_NRED__A */
435 0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */
436 0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */
439 0x06, 0x00, /* CE_REG_NE_MIXAVG__A */
440 0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */
443 0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */
444 0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */
447 0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */
448 0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
449 0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
452 0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */
453 0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
454 0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
457 0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */
458 0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */
461 0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */
462 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
463 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
465 WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
471 WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
472 WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
479 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
480 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
481 0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */
482 0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */
484 WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
485 WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
487 WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
488 WR16(EQ_REG_COMM_EXEC__A, 0x0001),
493 WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
499 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
500 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
501 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
502 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
503 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
504 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
505 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
506 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
507 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
508 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
509 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
512 WR16(EC_RS_EC_RAM__A, 0x0000),
513 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
519 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
520 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
521 0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */
522 0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */
523 0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */
524 0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */
527 0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
531 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
532 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
533 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
534 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
535 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
538 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
539 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
542 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
543 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
544 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
545 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
546 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
547 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
548 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
551 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
552 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
554 WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
555 WR16(EC_VD_REG_FORCE__A, 0x0002),
556 WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
557 WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
558 WR16(EC_OD_REG_SYNC__A, 0x0664),
559 WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
560 WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
580 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
581 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
582 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
583 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
584 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
585 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
586 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
587 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
588 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
589 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
590 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
593 WR16(EC_RS_EC_RAM__A, 0x0000),
594 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
596 WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
597 WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
598 WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
599 WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
604 WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
605 WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
606 WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
607 WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
608 WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
609 WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
610 WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
611 WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
613 WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
614 WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
615 WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
616 WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
617 WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
618 WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
621 WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
622 WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
623 WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
624 WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
625 WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
626 WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
627 WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
628 WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
630 WR16(B_EC_OD_REG_SYNC__A, 0x0664),
631 WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
635 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
636 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
637 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
638 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
639 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
640 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
641 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
642 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
643 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
644 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
645 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
648 WR16(EC_RS_EC_RAM__A, 0x0000),
649 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
651 WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
652 WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
653 WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
654 WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
660 WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
661 WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
664 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
665 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
666 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
667 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
668 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
671 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
672 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
675 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
676 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
677 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
678 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
679 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
680 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
681 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
684 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
685 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
687 WR16(EC_OD_REG_SYNC__A, 0x0664),
688 WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
689 WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
709 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
710 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
711 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
712 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
713 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
714 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
715 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
716 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
717 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
718 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
719 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
722 WR16(EC_RS_EC_RAM__A, 0x0000),
723 WR16(EC_RS_EC_RAM__A + 204, 0x0000),
725 WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
730 WR16(SC_COMM_EXEC__A, 0),
731 WR16(SC_COMM_STATE__A, 0),
734 WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
748 WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
749 WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
770 WR16(B_CC_REG_DIVERSITY__A, 0x0001),
771 WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
775 /* 0x2a ), *//* CE to PASS mux */
791 WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
792 WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
794 WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
795 WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
818 WR16(B_CC_REG_DIVERSITY__A, 0x0001),
857 WR16(B_CC_REG_DIVERSITY__A, 0x0000),
865 WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
866 WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
867 WR16(B_FE_AD_REG_INVEXT__A, 0x0),
868 WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
879 WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
880 WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
883 WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */