Lines Matching defs:drxj_data
408 struct drxj_data { struct
410 bool has_lna; /*< true if LNA (aka PGA) present */
411 bool has_oob; /*< true if OOB supported */
412 bool has_ntsc; /*< true if NTSC supported */
413 bool has_btsc; /*< true if BTSC supported */
414 bool has_smatx; /*< true if mat_tx is available */
415 bool has_smarx; /*< true if mat_rx is available */
416 bool has_gpio; /*< true if GPIO is available */
417 bool has_irqn; /*< true if IRQN is available */
419 u8 mfx; /*< metal fix */
422 bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal */
425 enum drx_standard standard; /*< current standard information */
426 enum drx_modulation constellation;
428 s32 frequency; /*< center signal frequency in KHz */
429 enum drx_bandwidth curr_bandwidth;
431 enum drx_mirror mirror; /*< current channel mirror */
434 u32 fec_bits_desired; /*< BER accounting period */
435 u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period */
436 u16 qam_vd_prescale; /*< Viterbi Measurement Prescale */
437 u16 qam_vd_period; /*< Viterbi Measurement period */
438 u16 fec_rs_plen; /*< defines RS BER measurement period */
439 u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale */
440 u16 fec_rs_period; /*< ReedSolomon Measurement period */
441 bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error */
442 u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error */
445 u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 */
446 u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */
447 u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 */
448 u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 */
449 u16 hi_cfg_transmit; /*< HI Configure() parameter 6 */
452 enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin */
453 enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin */
454 enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin */
455 enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin */
458 u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel */
459 bool pos_image; /*< True: positive image */
461 u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel */
464 u32 atv_cfg_changed_flags; /*< flag: flags cfg changes */
465 s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A */
466 s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A */
467 s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A */
468 s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A */
469 bool phase_correction_bypass;/*< flag: true=bypass */
470 s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A */
471 u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A */
472 bool enable_cvbs_output; /*< flag CVBS output enable */
473 bool enable_sif_output; /*< flag SIF output enable */
474 enum drxjsif_attenuation sif_attenuation;
477 struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config */
478 struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config */
479 struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config */
480 struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config */
483 u16 qam_pga_cfg; /*< qam PGA config */
484 u16 vsb_pga_cfg; /*< vsb PGA config */
487 struct drxj_cfg_pre_saw qam_pre_saw_cfg;
489 struct drxj_cfg_pre_saw vsb_pre_saw_cfg;
493 char v_text[2][12]; /*< allocated text versions */
494 struct drx_version v_version[2]; /*< allocated versions structs */
495 struct drx_version_list v_list_elements[2];
499 bool smart_ant_inverted;
502 u16 oob_trk_filter_cfg[8];
503 bool oob_power_on;
506 u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output */
507 bool disable_te_ihandling; /*< MPEG TS TEI handling */
508 bool bit_reverse_mpeg_outout;/*< MPEG output bit order */
509 enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate;
511 enum drxj_mpeg_start_width mpeg_start_width;
515 struct drxj_cfg_pre_saw atv_pre_saw_cfg;
517 struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config */
518 struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config */
519 u16 atv_pga_cfg; /*< atv pga config */
521 u32 curr_symbol_rate;
524 bool pdr_safe_mode; /*< PDR safe mode activated */
525 u16 pdr_safe_restore_val_gpio;
526 u16 pdr_safe_restore_val_v_sync;
527 u16 pdr_safe_restore_val_sma_rx;
528 u16 pdr_safe_restore_val_sma_tx;
552 (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) argument