Lines Matching +full:check +full:- +full:dco
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
52 /*-----------------------------------------------------------------------------
54 ----------------------------------------------------------------------------*/
74 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
200 /*-----------------------------------------------------------------------------
202 ----------------------------------------------------------------------------*/
204 /*-----------------------------------------------------------------------------
206 ----------------------------------------------------------------------------*/
208 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
404 * \brief RAM location of DCO config registers
437 #define AUD_VOLUME_DB_MIN -60
485 * x -> lowbyte(x), highbyte(x)
526 /*-----------------------------------------------------------------------------
528 ----------------------------------------------------------------------------*/
625 {-5,
633 {-50,
649 {-160,
774 { /* ATV RF-AGC */
782 4000 /* cut-off current */
784 { /* ATV IF-AGC */
829 (151875 - 0), /* system clock frequency in kHz */
944 0 /* dco */
951 0 /* dco */
975 /*-----------------------------------------------------------------------------
977 ----------------------------------------------------------------------------*/
1001 * struct drxu_code_block_hdr - Structure of the microcode block headers
1016 /*-----------------------------------------------------------------------------
1018 ----------------------------------------------------------------------------*/
1053 * This function is used to avoid floating-point calculations as they may
1056 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1058 * N and D can hold numbers up to width: 28-bits.
1061 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1063 * N: 0...(1<<28)-1 = 268435454
1064 * D: 0...(1<<28)-1
1065 * Q: 0...(1<<32)-1
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ in frac28()
1160 /* computing y in log(x/y) = log(x) - log(y) */ in log1_times100()
1161 if ((x & (((u32) (-1)) << (scale + 1))) == 0) { in log1_times100()
1162 for (k = scale; k > 0; k--) { in log1_times100()
1169 if ((x & (((u32) (-1)) << (scale + 1))) == 0) in log1_times100()
1175 Now x has binary point between bit[scale] and bit[scale-1] in log1_times100()
1182 x &= ((((u32) 1) << scale) - 1); in log1_times100()
1184 i = (u8) (x >> (scale - index_width)); in log1_times100()
1185 /* compute delta (x-a) */ in log1_times100()
1186 d = x & ((((u32) 1) << (scale - index_width)) - 1); in log1_times100()
1189 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width)); in log1_times100()
1204 * \param N nominator 16-bits.
1205 * \param D denominator 32-bits.
1209 * No check on D=0!
1265 -conversion to short address format
1266 -access to audio block
1276 TODO: check ignoring single/multimaster is ok for AUD access ?
1285 * \brief Check if this address is handled by the audio token ring interface.
1320 state = r_dev_addr->user_data; in drxbsp_i2c_write_read()
1321 msg[0].addr = r_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1328 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1329 msg[0].addr = w_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1336 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1337 msg[0].addr = w_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1341 msg[1].addr = r_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1348 if (state->i2c == NULL) { in drxbsp_i2c_write_read()
1352 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { in drxbsp_i2c_write_read()
1354 return -EREMOTEIO; in drxbsp_i2c_write_read()
1361 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1363 if (state->i2c == NULL) in drxbsp_i2c_write_read()
1366 msg[0].addr = w_dev_addr->i2c_addr; in drxbsp_i2c_write_read()
1370 msg[1].addr = r_dev_addr->i2c_addr; in drxbsp_i2c_write_read()
1377 w_dev_addr->i2c_addr, state->i2c, w_count, r_count); in drxbsp_i2c_write_read()
1379 if (i2c_transfer(state->i2c, msg, 2) != 2) { in drxbsp_i2c_write_read()
1381 return -EREMOTEIO; in drxbsp_i2c_write_read()
1392 * struct i2c_device_addr *dev_addr, -- address of I2C device
1393 * u32 addr, -- address of chip register/memory
1394 * u16 datasize, -- number of bytes to read
1395 * u8 *data, -- data to receive
1396 * u32 flags) -- special device flags
1408 * - 0 if reading was successful
1410 * - -EIO if anything went wrong
1424 /* Check parameters ******************************************************* */ in drxdap_fasi_read_block()
1426 return -EINVAL; in drxdap_fasi_read_block()
1428 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + in drxdap_fasi_read_block()
1436 return -EINVAL; in drxdap_fasi_read_block()
1494 datasize -= todo; in drxdap_fasi_read_block()
1504 * struct i2c_device_addr *dev_addr, -- address of I2C device
1505 * u32 addr, -- address of chip register/memory
1506 * u16 *data, -- data to receive
1507 * u32 flags) -- special device flags
1509 * Read one 16-bit register or memory location. The data received back is
1513 * - 0 if reading was successful
1515 * - -EIO if anything went wrong
1527 return -EINVAL; in drxdap_fasi_read_reg16()
1537 * struct i2c_device_addr *dev_addr, -- address of I2C device
1538 * u32 addr, -- address of chip register/memory
1539 * u32 *data, -- data to receive
1540 * u32 flags) -- special device flags
1542 * Read one 32-bit register or memory location. The data received back is
1546 * - 0 if reading was successful
1548 * - -EIO if anything went wrong
1560 return -EINVAL; in drxdap_fasi_read_reg32()
1572 * struct i2c_device_addr *dev_addr, -- address of I2C device
1573 * u32 addr, -- address of chip register/memory
1574 * u16 datasize, -- number of bytes to read
1575 * u8 *data, -- data to receive
1576 * u32 flags) -- special device flags
1586 * - 0 if writing was successful
1587 * - -EIO if anything went wrong
1597 int st = -EIO; in drxdap_fasi_write_block()
1602 /* Check parameters ******************************************************* */ in drxdap_fasi_write_block()
1604 return -EINVAL; in drxdap_fasi_write_block()
1606 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + in drxdap_fasi_write_block()
1614 return -EINVAL; in drxdap_fasi_write_block()
1623 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; in drxdap_fasi_write_block()
1668 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); in drxdap_fasi_write_block()
1670 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; in drxdap_fasi_write_block()
1700 datasize -= todo; in drxdap_fasi_write_block()
1711 * struct i2c_device_addr *dev_addr, -- address of I2C device
1712 * u32 addr, -- address of chip register/memory
1713 * u16 data, -- data to send
1714 * u32 flags) -- special device flags
1716 * Write one 16-bit register or memory location. The data being written is
1720 * - 0 if writing was successful
1721 * - -EIO if anything went wrong
1740 * struct i2c_device_addr *dev_addr, -- address of I2C device
1741 * u32 waddr, -- address of chip register/memory
1742 * u32 raddr, -- chip address to read back from
1743 * u16 wdata, -- data to send
1744 * u16 *rdata) -- data to receive back
1746 * Write 16-bit data, then read back the original contents of that location.
1756 * - 0 if reading was successful
1758 * - -EIO if anything went wrong
1767 int rc = -EIO; in drxdap_fasi_read_modify_write_reg16()
1771 return -EINVAL; in drxdap_fasi_read_modify_write_reg16()
1784 * struct i2c_device_addr *dev_addr, -- address of I2C device
1785 * u32 addr, -- address of chip register/memory
1786 * u32 data, -- data to send
1787 * u32 flags) -- special device flags
1789 * Write one 32-bit register or memory location. The data being written is
1793 * - 0 if writing was successful
1794 * - -EIO if anything went wrong
1824 * \retval -EIO Timeout, I2C error, illegal bank
1843 return -EINVAL; in drxj_dap_rm_write_reg16short()
1901 * \retval -EIO Timeout, I2C error, illegal bank
1913 int stat = -EIO; in drxj_dap_read_aud_reg16()
1917 stat = -EINVAL; in drxj_dap_read_aud_reg16()
1937 delta_timer = current_timer - start_timer; in drxj_dap_read_aud_reg16()
1939 stat = -EIO; in drxj_dap_read_aud_reg16()
1962 delta_timer = current_timer - start_timer; in drxj_dap_read_aud_reg16()
1964 stat = -EIO; in drxj_dap_read_aud_reg16()
1985 int stat = -EIO; in drxj_dap_read_reg16()
1987 /* Check param */ in drxj_dap_read_reg16()
1989 return -EINVAL; in drxj_dap_read_reg16()
2008 * \retval -EIO Timeout, I2C error, illegal bank
2016 int stat = -EIO; in drxj_dap_write_aud_reg16()
2020 stat = -EINVAL; in drxj_dap_write_aud_reg16()
2041 delta_timer = current_timer - start_timer; in drxj_dap_write_aud_reg16()
2043 stat = -EIO; in drxj_dap_write_aud_reg16()
2063 int stat = -EIO; in drxj_dap_write_reg16()
2065 /* Check param */ in drxj_dap_write_reg16()
2067 return -EINVAL; in drxj_dap_write_reg16()
2098 * \retval -EIO Timeout, I2C error, illegal bank
2113 /* Parameter check */ in drxj_dap_atomic_read_write_block()
2115 return -EINVAL; in drxj_dap_atomic_read_write_block()
2124 hi_cmd.param3 = (u16) ((datasize / 2) - 1); in drxj_dap_atomic_read_write_block()
2189 return -EINVAL; in drxj_dap_atomic_read_reg32()
2230 * enable/disable should not need re-configuration of the HI.
2240 ext_attr = (struct drxj_data *) demod->my_ext_attr; in hi_cfg_command()
2244 hi_cmd.param2 = ext_attr->hi_cfg_timing_div; in hi_cfg_command()
2245 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay; in hi_cfg_command()
2246 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key; in hi_cfg_command()
2247 hi_cmd.param5 = ext_attr->hi_cfg_ctrl; in hi_cfg_command()
2248 hi_cmd.param6 = ext_attr->hi_cfg_transmit; in hi_cfg_command()
2250 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in hi_cfg_command()
2257 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); in hi_cfg_command()
2285 switch (cmd->cmd) { in hi_command()
2289 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); in hi_command()
2294 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); in hi_command()
2299 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); in hi_command()
2304 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); in hi_command()
2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); in hi_command()
2316 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); in hi_command()
2327 return -EINVAL; in hi_command()
2331 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); in hi_command()
2337 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) in hi_command()
2341 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && in hi_command()
2342 (((cmd-> in hi_command()
2350 rc = -ETIMEDOUT; in hi_command()
2382 * \retval -EIO Failure.
2396 ext_attr = (struct drxj_data *) demod->my_ext_attr; in init_hi()
2397 common_attr = (struct drx_common_attr *) demod->my_common_attr; in init_hi()
2398 dev_addr = demod->my_i2c_dev_addr; in init_hi()
2409 ext_attr->hi_cfg_timing_div = in init_hi()
2410 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; in init_hi()
2412 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_hi()
2413 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_hi()
2417 ext_attr->hi_cfg_bridge_delay = in init_hi()
2418 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) / in init_hi()
2421 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) in init_hi()
2422 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; in init_hi()
2424 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << in init_hi()
2429 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY; in init_hi()
2431 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); in init_hi()
2433 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; in init_hi()
2463 * \retval -EIO Failure
2466 * * common_attr->osc_clock_freq
2467 * * ext_attr->has_lna
2468 * * ext_attr->has_ntsc
2469 * * ext_attr->has_btsc
2470 * * ext_attr->has_oob
2483 common_attr = (struct drx_common_attr *) demod->my_common_attr; in get_device_capabilities()
2484 ext_attr = (struct drxj_data *) demod->my_ext_attr; in get_device_capabilities()
2485 dev_addr = demod->my_i2c_dev_addr; in get_device_capabilities()
2509 common_attr->osc_clock_freq = 27000; in get_device_capabilities()
2513 common_attr->osc_clock_freq = 20250; in get_device_capabilities()
2517 common_attr->osc_clock_freq = 4000; in get_device_capabilities()
2520 return -EIO; in get_device_capabilities()
2532 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF); in get_device_capabilities()
2553 ext_attr->has_lna = true; in get_device_capabilities()
2554 ext_attr->has_ntsc = false; in get_device_capabilities()
2555 ext_attr->has_btsc = false; in get_device_capabilities()
2556 ext_attr->has_oob = false; in get_device_capabilities()
2557 ext_attr->has_smatx = true; in get_device_capabilities()
2558 ext_attr->has_smarx = false; in get_device_capabilities()
2559 ext_attr->has_gpio = false; in get_device_capabilities()
2560 ext_attr->has_irqn = false; in get_device_capabilities()
2563 ext_attr->has_lna = false; in get_device_capabilities()
2564 ext_attr->has_ntsc = false; in get_device_capabilities()
2565 ext_attr->has_btsc = false; in get_device_capabilities()
2566 ext_attr->has_oob = false; in get_device_capabilities()
2567 ext_attr->has_smatx = true; in get_device_capabilities()
2568 ext_attr->has_smarx = false; in get_device_capabilities()
2569 ext_attr->has_gpio = false; in get_device_capabilities()
2570 ext_attr->has_irqn = false; in get_device_capabilities()
2573 ext_attr->has_lna = true; in get_device_capabilities()
2574 ext_attr->has_ntsc = true; in get_device_capabilities()
2575 ext_attr->has_btsc = false; in get_device_capabilities()
2576 ext_attr->has_oob = false; in get_device_capabilities()
2577 ext_attr->has_smatx = true; in get_device_capabilities()
2578 ext_attr->has_smarx = true; in get_device_capabilities()
2579 ext_attr->has_gpio = true; in get_device_capabilities()
2580 ext_attr->has_irqn = false; in get_device_capabilities()
2583 ext_attr->has_lna = false; in get_device_capabilities()
2584 ext_attr->has_ntsc = true; in get_device_capabilities()
2585 ext_attr->has_btsc = false; in get_device_capabilities()
2586 ext_attr->has_oob = false; in get_device_capabilities()
2587 ext_attr->has_smatx = true; in get_device_capabilities()
2588 ext_attr->has_smarx = true; in get_device_capabilities()
2589 ext_attr->has_gpio = true; in get_device_capabilities()
2590 ext_attr->has_irqn = false; in get_device_capabilities()
2593 ext_attr->has_lna = true; in get_device_capabilities()
2594 ext_attr->has_ntsc = true; in get_device_capabilities()
2595 ext_attr->has_btsc = true; in get_device_capabilities()
2596 ext_attr->has_oob = false; in get_device_capabilities()
2597 ext_attr->has_smatx = true; in get_device_capabilities()
2598 ext_attr->has_smarx = true; in get_device_capabilities()
2599 ext_attr->has_gpio = true; in get_device_capabilities()
2600 ext_attr->has_irqn = false; in get_device_capabilities()
2603 ext_attr->has_lna = false; in get_device_capabilities()
2604 ext_attr->has_ntsc = true; in get_device_capabilities()
2605 ext_attr->has_btsc = true; in get_device_capabilities()
2606 ext_attr->has_oob = false; in get_device_capabilities()
2607 ext_attr->has_smatx = true; in get_device_capabilities()
2608 ext_attr->has_smarx = true; in get_device_capabilities()
2609 ext_attr->has_gpio = true; in get_device_capabilities()
2610 ext_attr->has_irqn = false; in get_device_capabilities()
2613 ext_attr->has_lna = true; in get_device_capabilities()
2614 ext_attr->has_ntsc = false; in get_device_capabilities()
2615 ext_attr->has_btsc = false; in get_device_capabilities()
2616 ext_attr->has_oob = true; in get_device_capabilities()
2617 ext_attr->has_smatx = true; in get_device_capabilities()
2618 ext_attr->has_smarx = true; in get_device_capabilities()
2619 ext_attr->has_gpio = true; in get_device_capabilities()
2620 ext_attr->has_irqn = true; in get_device_capabilities()
2623 ext_attr->has_lna = false; in get_device_capabilities()
2624 ext_attr->has_ntsc = true; in get_device_capabilities()
2625 ext_attr->has_btsc = true; in get_device_capabilities()
2626 ext_attr->has_oob = true; in get_device_capabilities()
2627 ext_attr->has_smatx = true; in get_device_capabilities()
2628 ext_attr->has_smarx = true; in get_device_capabilities()
2629 ext_attr->has_gpio = true; in get_device_capabilities()
2630 ext_attr->has_irqn = true; in get_device_capabilities()
2633 ext_attr->has_lna = true; in get_device_capabilities()
2634 ext_attr->has_ntsc = true; in get_device_capabilities()
2635 ext_attr->has_btsc = true; in get_device_capabilities()
2636 ext_attr->has_oob = true; in get_device_capabilities()
2637 ext_attr->has_smatx = true; in get_device_capabilities()
2638 ext_attr->has_smarx = true; in get_device_capabilities()
2639 ext_attr->has_gpio = true; in get_device_capabilities()
2640 ext_attr->has_irqn = true; in get_device_capabilities()
2643 ext_attr->has_lna = false; in get_device_capabilities()
2644 ext_attr->has_ntsc = true; in get_device_capabilities()
2645 ext_attr->has_btsc = true; in get_device_capabilities()
2646 ext_attr->has_oob = true; in get_device_capabilities()
2647 ext_attr->has_smatx = true; in get_device_capabilities()
2648 ext_attr->has_smarx = true; in get_device_capabilities()
2649 ext_attr->has_gpio = true; in get_device_capabilities()
2650 ext_attr->has_irqn = true; in get_device_capabilities()
2654 return -EIO; in get_device_capabilities()
2669 * \retval -EIO Failure, I2C or max retries reached
2684 dev_addr = demod->my_i2c_dev_addr; in power_up_device()
2686 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id; in power_up_device()
2687 wake_up_addr.user_data = dev_addr->user_data; in power_up_device()
2709 return -EIO; in power_up_device()
2714 /*----------------------------------------------------------------------------*/
2715 /* MPEG Output Configuration Functions - begin */
2716 /*----------------------------------------------------------------------------*/
2748 /* check arguments */ in ctrl_set_cfg_mpeg_output()
2750 return -EINVAL; in ctrl_set_cfg_mpeg_output()
2752 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_mpeg_output()
2753 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_mpeg_output()
2754 common_attr = (struct drx_common_attr *) demod->my_common_attr; in ctrl_set_cfg_mpeg_output()
2756 if (cfg_data->enable_mpeg_output == true) { in ctrl_set_cfg_mpeg_output()
2759 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2774 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2821 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2838 return -EIO; in ctrl_set_cfg_mpeg_output()
2839 } /* ext_attr->constellation */ in ctrl_set_cfg_mpeg_output()
2843 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; in ctrl_set_cfg_mpeg_output()
2871 if (cfg_data->static_clk == true) { in ctrl_set_cfg_mpeg_output()
2899 /* Check insertion of the Reed-Solomon parity bytes */ in ctrl_set_cfg_mpeg_output()
2910 if (cfg_data->insert_rs_byte == true) { in ctrl_set_cfg_mpeg_output()
2915 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2921 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2929 return -EIO; in ctrl_set_cfg_mpeg_output()
2934 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ in ctrl_set_cfg_mpeg_output()
2938 (u32) (common_attr->sys_clock_freq / 8))) / in ctrl_set_cfg_mpeg_output()
2942 return -EIO; in ctrl_set_cfg_mpeg_output()
2943 } /* ext_attr->standard */ in ctrl_set_cfg_mpeg_output()
2950 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2956 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2964 return -EIO; in ctrl_set_cfg_mpeg_output()
2969 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */ in ctrl_set_cfg_mpeg_output()
2973 (u32) (common_attr->sys_clock_freq / 8))) / in ctrl_set_cfg_mpeg_output()
2977 return -EIO; in ctrl_set_cfg_mpeg_output()
2978 } /* ext_attr->standard */ in ctrl_set_cfg_mpeg_output()
2981 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */ in ctrl_set_cfg_mpeg_output()
2983 } else { /* MPEG data output is serial -> set ipr_mode[0] */ in ctrl_set_cfg_mpeg_output()
2988 if (cfg_data->invert_data == true) in ctrl_set_cfg_mpeg_output()
2993 if (cfg_data->invert_err == true) in ctrl_set_cfg_mpeg_output()
2998 if (cfg_data->invert_str == true) in ctrl_set_cfg_mpeg_output()
3003 if (cfg_data->invert_val == true) in ctrl_set_cfg_mpeg_output()
3008 if (cfg_data->invert_clk == true) in ctrl_set_cfg_mpeg_output()
3014 if (cfg_data->static_clk == true) { /* Static mode */ in ctrl_set_cfg_mpeg_output()
3022 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
3025 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3031 if (cfg_data->insert_rs_byte == true) { in ctrl_set_cfg_mpeg_output()
3035 if (ext_attr->curr_symbol_rate >= in ctrl_set_cfg_mpeg_output()
3045 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3050 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3054 return -EIO; in ctrl_set_cfg_mpeg_output()
3057 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + in ctrl_set_cfg_mpeg_output()
3060 frac28(bit_rate, common_attr->sys_clock_freq * 1000); in ctrl_set_cfg_mpeg_output()
3087 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) in ctrl_set_cfg_mpeg_output()
3088 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; in ctrl_set_cfg_mpeg_output()
3167 …if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to outp… in ctrl_set_cfg_mpeg_output()
3212 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ in ctrl_set_cfg_mpeg_output()
3343 /* save values for restore after re-acquire */ in ctrl_set_cfg_mpeg_output()
3344 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output; in ctrl_set_cfg_mpeg_output()
3351 /*----------------------------------------------------------------------------*/
3354 /*----------------------------------------------------------------------------*/
3355 /* MPEG Output Configuration Functions - end */
3356 /*----------------------------------------------------------------------------*/
3358 /*----------------------------------------------------------------------------*/
3359 /* miscellaneous configurations - begin */
3360 /*----------------------------------------------------------------------------*/
3380 dev_addr = demod->my_i2c_dev_addr; in set_mpegtei_handling()
3381 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_mpegtei_handling()
3405 if (ext_attr->disable_te_ihandling) { in set_mpegtei_handling()
3434 /*----------------------------------------------------------------------------*/
3437 * \brief Set MPEG output bit-endian settings.
3451 dev_addr = demod->my_i2c_dev_addr; in bit_reverse_mpeg_output()
3452 ext_attr = (struct drxj_data *) demod->my_ext_attr; in bit_reverse_mpeg_output()
3463 if (ext_attr->bit_reverse_mpeg_outout) in bit_reverse_mpeg_output()
3477 /*----------------------------------------------------------------------------*/
3495 dev_addr = demod->my_i2c_dev_addr; in set_mpeg_start_width()
3496 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_mpeg_start_width()
3497 common_attr = demod->my_common_attr; in set_mpeg_start_width()
3499 if ((common_attr->mpeg_cfg.static_clk == true) in set_mpeg_start_width()
3500 && (common_attr->mpeg_cfg.enable_parallel == false)) { in set_mpeg_start_width()
3507 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) in set_mpeg_start_width()
3521 /*----------------------------------------------------------------------------*/
3522 /* miscellaneous configurations - end */
3523 /*----------------------------------------------------------------------------*/
3525 /*----------------------------------------------------------------------------*/
3526 /* UIO Configuration Functions - begin */
3527 /*----------------------------------------------------------------------------*/
3541 return -EINVAL; in ctrl_set_uio_cfg()
3543 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_uio_cfg()
3546 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_set_uio_cfg()
3551 switch (uio_cfg->uio) { in ctrl_set_uio_cfg()
3554 /* DRX_UIO1: SMA_TX UIO-1 */ in ctrl_set_uio_cfg()
3555 if (!ext_attr->has_smatx) in ctrl_set_uio_cfg()
3556 return -EIO; in ctrl_set_uio_cfg()
3557 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3561 ext_attr->uio_sma_tx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3564 ext_attr->uio_sma_tx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3565 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3566 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3573 return -EINVAL; in ctrl_set_uio_cfg()
3574 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3578 /* DRX_UIO2: SMA_RX UIO-2 */ in ctrl_set_uio_cfg()
3579 if (!ext_attr->has_smarx) in ctrl_set_uio_cfg()
3580 return -EIO; in ctrl_set_uio_cfg()
3581 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3584 ext_attr->uio_sma_rx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3587 ext_attr->uio_sma_rx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3588 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3589 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3596 return -EINVAL; in ctrl_set_uio_cfg()
3597 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3601 /* DRX_UIO3: GPIO UIO-3 */ in ctrl_set_uio_cfg()
3602 if (!ext_attr->has_gpio) in ctrl_set_uio_cfg()
3603 return -EIO; in ctrl_set_uio_cfg()
3604 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3607 ext_attr->uio_gpio_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3610 ext_attr->uio_gpio_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3611 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3612 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3619 return -EINVAL; in ctrl_set_uio_cfg()
3620 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3624 /* DRX_UIO4: IRQN UIO-4 */ in ctrl_set_uio_cfg()
3625 if (!ext_attr->has_irqn) in ctrl_set_uio_cfg()
3626 return -EIO; in ctrl_set_uio_cfg()
3627 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3629 ext_attr->uio_irqn_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3632 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3633 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3638 ext_attr->uio_irqn_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3642 return -EINVAL; in ctrl_set_uio_cfg()
3643 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3647 return -EINVAL; in ctrl_set_uio_cfg()
3648 } /* switch ( uio_cfg->uio ) */ in ctrl_set_uio_cfg()
3651 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_uio_cfg()
3678 return -EINVAL; in ctrl_uio_write()
3680 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_uio_write()
3683 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_uio_write()
3688 switch (uio_data->uio) { in ctrl_uio_write()
3691 /* DRX_UIO1: SMA_TX UIO-1 */ in ctrl_uio_write()
3692 if (!ext_attr->has_smatx) in ctrl_uio_write()
3693 return -EIO; in ctrl_uio_write()
3694 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3695 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { in ctrl_uio_write()
3696 return -EIO; in ctrl_uio_write()
3704 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3705 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3712 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3717 if (!uio_data->value) in ctrl_uio_write()
3718 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ in ctrl_uio_write()
3720 value |= 0x8000; /* write one to 15th bit - 1st UIO */ in ctrl_uio_write()
3723 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3731 /* DRX_UIO2: SMA_RX UIO-2 */ in ctrl_uio_write()
3732 if (!ext_attr->has_smarx) in ctrl_uio_write()
3733 return -EIO; in ctrl_uio_write()
3734 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3735 return -EIO; in ctrl_uio_write()
3743 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3744 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3751 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3756 if (!uio_data->value) in ctrl_uio_write()
3757 value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ in ctrl_uio_write()
3759 value |= 0x4000; /* write one to 14th bit - 2nd UIO */ in ctrl_uio_write()
3762 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3770 /* DRX_UIO3: ASEL UIO-3 */ in ctrl_uio_write()
3771 if (!ext_attr->has_gpio) in ctrl_uio_write()
3772 return -EIO; in ctrl_uio_write()
3773 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3774 return -EIO; in ctrl_uio_write()
3782 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3783 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3790 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); in ctrl_uio_write()
3795 if (!uio_data->value) in ctrl_uio_write()
3796 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ in ctrl_uio_write()
3798 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ in ctrl_uio_write()
3801 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); in ctrl_uio_write()
3809 /* DRX_UIO4: IRQN UIO-4 */ in ctrl_uio_write()
3810 if (!ext_attr->has_irqn) in ctrl_uio_write()
3811 return -EIO; in ctrl_uio_write()
3813 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3814 return -EIO; in ctrl_uio_write()
3822 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3823 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3830 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3835 if (uio_data->value == false) in ctrl_uio_write()
3836 value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ in ctrl_uio_write()
3838 value |= 0x1000; /* write one to 12th bit - 4th UIO */ in ctrl_uio_write()
3841 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3849 return -EINVAL; in ctrl_uio_write()
3850 } /* switch ( uio_data->uio ) */ in ctrl_uio_write()
3853 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_uio_write()
3864 /*---------------------------------------------------------------------------*/
3865 /* UIO Configuration Functions - end */
3866 /*---------------------------------------------------------------------------*/
3868 /*----------------------------------------------------------------------------*/
3869 /* I2C Bridge Functions - begin */
3870 /*----------------------------------------------------------------------------*/
3885 /* check arguments */ in ctrl_i2c_bridge()
3887 return -EINVAL; in ctrl_i2c_bridge()
3896 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in ctrl_i2c_bridge()
3899 /*----------------------------------------------------------------------------*/
3900 /* I2C Bridge Functions - end */
3901 /*----------------------------------------------------------------------------*/
3903 /*----------------------------------------------------------------------------*/
3904 /* Smart antenna Functions - begin */
3905 /*----------------------------------------------------------------------------*/
3921 dev_addr = demod->my_i2c_dev_addr; in smart_ant_init()
3922 ext_attr = (struct drxj_data *) demod->my_ext_attr; in smart_ant_init()
3925 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in smart_ant_init()
3936 if (ext_attr->smart_ant_inverted) { in smart_ant_init()
3956 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); in smart_ant_init()
3961 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); in smart_ant_init()
3968 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in smart_ant_init()
3985 /* Check param */ in scu_command()
3987 return -EINVAL; in scu_command()
3996 return -EIO; in scu_command()
3998 switch (cmd->parameter_len) { in scu_command()
4000 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); in scu_command()
4007 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); in scu_command()
4014 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); in scu_command()
4021 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); in scu_command()
4028 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); in scu_command()
4039 return -EIO; in scu_command()
4041 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); in scu_command()
4061 return -EIO; in scu_command()
4064 if ((cmd->result_len > 0) && (cmd->result != NULL)) { in scu_command()
4067 switch (cmd->result_len) { in scu_command()
4069 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); in scu_command()
4076 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); in scu_command()
4083 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); in scu_command()
4090 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); in scu_command()
4101 return -EIO; in scu_command()
4104 /* Check if an error was reported by SCU */ in scu_command()
4105 err = cmd->result[0]; in scu_command()
4107 /* check a few fixed error codes */ in scu_command()
4113 return -EINVAL; in scu_command()
4117 return -EIO; in scu_command()
4137 * \retval -EIO Timeout, I2C error, illegal bank
4140 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4150 /* Parameter check */ in drxj_dap_scu_atomic_read_write_block()
4152 return -EINVAL; in drxj_dap_scu_atomic_read_write_block()
4214 return -EINVAL; in drxj_dap_scu_atomic_read_reg16()
4248 /* -------------------------------------------------------------------------- */
4255 * \retval -EIO Failure: I2C error
4264 dev_addr = demod->my_i2c_dev_addr; in adc_sync_measurement()
4314 * \retval -EIO Failure: I2C error or failure to synchronize
4327 dev_addr = demod->my_i2c_dev_addr; in adc_synchronization()
4361 return -EIO; in adc_synchronization()
4408 dev_addr = demod->my_i2c_dev_addr; in init_agc()
4409 common_attr = (struct drx_common_attr *) demod->my_common_attr; in init_agc()
4410 ext_attr = (struct drxj_data *) demod->my_ext_attr; in init_agc()
4412 switch (ext_attr->standard) { in init_agc()
4415 clp_dir_to = (u16) (-9); in init_agc()
4417 sns_dir_to = (u16) (-9); in init_agc()
4418 ki_innergain_min = (u16) (-32768); in init_agc()
4490 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg); in init_agc()
4491 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg); in init_agc()
4499 clp_dir_to = (u16) (-5); in init_agc()
4501 sns_dir_to = (u16) (-3); in init_agc()
4558 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); in init_agc()
4559 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); in init_agc()
4560 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); in init_agc()
4580 return -EINVAL; in init_agc()
4584 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); in init_agc()
4589 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); in init_agc()
4608 } /* set to p_agc_settings->top before */ in init_agc()
4715 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; in init_agc()
4716 if (common_attr->tuner_rf_agc_pol == true) in init_agc()
4717 agc_rf = 0x87ff - agc_rf; in init_agc()
4720 if (common_attr->tuner_if_agc_pol == true) in init_agc()
4721 agc_rf = 0x87ff - agc_rf; in init_agc()
4765 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_frequency()
4766 struct drxj_data *ext_attr = demod->my_ext_attr; in set_frequency()
4771 s32 rf_freq_residual = -1 * tuner_freq_offset; in set_frequency()
4782 rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false; in set_frequency()
4783 tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true; in set_frequency()
4788 switch (ext_attr->standard) { in set_frequency()
4810 return -EINVAL; in set_frequency()
4812 intermediate_freq = demod->my_common_attr->intermediate_freq; in set_frequency()
4813 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; in set_frequency()
4817 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift; in set_frequency()
4820 adc_freq = sampling_frequency - if_freq_actual; in set_frequency()
4843 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; in set_frequency()
4844 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); in set_frequency()
4858 * \retval -EINVAL sig_strength is NULL.
4859 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4871 ext_attr = (struct drxj_data *) demod->my_ext_attr; in get_acc_pkt_err()
4872 dev_addr = demod->my_i2c_dev_addr; in get_acc_pkt_err()
4879 if (ext_attr->reset_pkt_err_acc) { in get_acc_pkt_err()
4882 ext_attr->reset_pkt_err_acc = false; in get_acc_pkt_err()
4886 pkt_err += 0xffff - last_pkt_err; in get_acc_pkt_err()
4889 pkt_err += (data - last_pkt_err); in get_acc_pkt_err()
4921 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_agc_rf()
4922 dev_addr = demod->my_i2c_dev_addr; in set_agc_rf()
4923 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_agc_rf()
4934 if ((ext_attr->standard == agc_settings->standard) || in set_agc_rf()
4935 (DRXJ_ISQAMSTD(ext_attr->standard) && in set_agc_rf()
4936 DRXJ_ISQAMSTD(agc_settings->standard)) || in set_agc_rf()
4937 (DRXJ_ISATVSTD(ext_attr->standard) && in set_agc_rf()
4938 DRXJ_ISATVSTD(agc_settings->standard))) { in set_agc_rf()
4941 switch (agc_settings->ctrl_mode) { in set_agc_rf()
4964 if (ext_attr->standard == DRX_STANDARD_8VSB) in set_agc_rf()
4966 else if (DRXJ_ISQAMSTD(ext_attr->standard)) in set_agc_rf()
4971 if (common_attr->tuner_rf_agc_pol) in set_agc_rf()
4988 …rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAG… in set_agc_rf()
4994 if (agc_settings->standard == DRX_STANDARD_8VSB) in set_agc_rf()
4995 p_agc_settings = &(ext_attr->vsb_if_agc_cfg); in set_agc_rf()
4996 else if (DRXJ_ISQAMSTD(agc_settings->standard)) in set_agc_rf()
4997 p_agc_settings = &(ext_attr->qam_if_agc_cfg); in set_agc_rf()
4998 else if (DRXJ_ISATVSTD(agc_settings->standard)) in set_agc_rf()
4999 p_agc_settings = &(ext_attr->atv_if_agc_cfg); in set_agc_rf()
5001 return -EINVAL; in set_agc_rf()
5003 /* Set TOP, only if IF-AGC is in AUTO mode */ in set_agc_rf()
5004 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { in set_agc_rf()
5005 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); in set_agc_rf()
5010 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); in set_agc_rf()
5017 /* Cut-Off current */ in set_agc_rf()
5018 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); in set_agc_rf()
5046 if (common_attr->tuner_rf_agc_pol) in set_agc_rf()
5057 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); in set_agc_rf()
5092 return -EINVAL; in set_agc_rf()
5093 } /* switch ( agcsettings->ctrl_mode ) */ in set_agc_rf()
5097 switch (agc_settings->standard) { in set_agc_rf()
5099 ext_attr->vsb_rf_agc_cfg = *agc_settings; in set_agc_rf()
5105 ext_attr->qam_rf_agc_cfg = *agc_settings; in set_agc_rf()
5109 return -EIO; in set_agc_rf()
5135 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_agc_if()
5136 dev_addr = demod->my_i2c_dev_addr; in set_agc_if()
5137 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_agc_if()
5148 if ((ext_attr->standard == agc_settings->standard) || in set_agc_if()
5149 (DRXJ_ISQAMSTD(ext_attr->standard) && in set_agc_if()
5150 DRXJ_ISQAMSTD(agc_settings->standard)) || in set_agc_if()
5151 (DRXJ_ISATVSTD(ext_attr->standard) && in set_agc_if()
5152 DRXJ_ISATVSTD(agc_settings->standard))) { in set_agc_if()
5155 switch (agc_settings->ctrl_mode) { in set_agc_if()
5178 if (ext_attr->standard == DRX_STANDARD_8VSB) in set_agc_if()
5180 else if (DRXJ_ISQAMSTD(ext_attr->standard)) in set_agc_if()
5185 if (common_attr->tuner_if_agc_pol) in set_agc_if()
5202 …rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IA… in set_agc_if()
5208 if (agc_settings->standard == DRX_STANDARD_8VSB) in set_agc_if()
5209 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg); in set_agc_if()
5210 else if (DRXJ_ISQAMSTD(agc_settings->standard)) in set_agc_if()
5211 p_agc_settings = &(ext_attr->qam_rf_agc_cfg); in set_agc_if()
5212 else if (DRXJ_ISATVSTD(agc_settings->standard)) in set_agc_if()
5213 p_agc_settings = &(ext_attr->atv_rf_agc_cfg); in set_agc_if()
5215 return -EINVAL; in set_agc_if()
5218 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { in set_agc_if()
5219 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); in set_agc_if()
5224 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); in set_agc_if()
5266 if (common_attr->tuner_if_agc_pol) in set_agc_if()
5277 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); in set_agc_if()
5314 return -EINVAL; in set_agc_if()
5315 } /* switch ( agcsettings->ctrl_mode ) */ in set_agc_if()
5317 /* always set the top to support configurations without if-loop */ in set_agc_if()
5318 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); in set_agc_if()
5326 switch (agc_settings->standard) { in set_agc_if()
5328 ext_attr->vsb_if_agc_cfg = *agc_settings; in set_agc_if()
5334 ext_attr->qam_if_agc_cfg = *agc_settings; in set_agc_if()
5338 return -EIO; in set_agc_if()
5359 dev_addr = demod->my_i2c_dev_addr; in set_iqm_af()
5401 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_vsb()
5689 dev_addr = demod->my_i2c_dev_addr; in set_vsb_leak_n_gain()
5723 DRXJ_16TO8(-2), /* re0 */ in set_vsb()
5726 DRXJ_16TO8(-4), /* re3 */ in set_vsb()
5729 DRXJ_16TO8(-3), /* re6 */ in set_vsb()
5730 DRXJ_16TO8(-3), /* re7 */ in set_vsb()
5733 DRXJ_16TO8(-9), /* re10 */ in set_vsb()
5736 DRXJ_16TO8(-9), /* re13 */ in set_vsb()
5737 DRXJ_16TO8(-15), /* re14 */ in set_vsb()
5740 DRXJ_16TO8(-29), /* re17 */ in set_vsb()
5741 DRXJ_16TO8(-22), /* re18 */ in set_vsb()
5744 DRXJ_16TO8(-70), /* re21 */ in set_vsb()
5745 DRXJ_16TO8(-28), /* re22 */ in set_vsb()
5748 DRXJ_16TO8(-201), /* re25 */ in set_vsb()
5749 DRXJ_16TO8(-31), /* re26 */ in set_vsb()
5753 dev_addr = demod->my_i2c_dev_addr; in set_vsb()
5754 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_vsb()
5755 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_vsb()
5822 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; in set_vsb()
5823 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); in set_vsb()
6038 /* B-Input to ADC, PGA+filter in standby */ in set_vsb()
6039 if (!ext_attr->has_lna) { in set_vsb()
6064 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); in set_vsb()
6069 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); in set_vsb()
6079 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; in set_vsb()
6086 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); in set_vsb()
6113 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in set_vsb()
6241 return -EIO; in get_vsb_post_rs_pck_err()
6285 return -EIO; in get_vs_bpost_viterbi_ber()
6288 (bit_errors_exp - 3) : bit_errors_exp); in get_vs_bpost_viterbi_ber()
6310 return -EIO; in get_vs_bpre_viterbi_ber()
6334 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); in get_vsbmer()
6368 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_qam()
6370 struct drx_common_attr *common_attr = demod->my_common_attr; in power_down_qam()
6440 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in power_down_qam()
6465 * The implementation does not check this.
6467 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6491 dev_addr = demod->my_i2c_dev_addr; in set_qam_measurement()
6492 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam_measurement()
6494 fec_bits_desired = ext_attr->fec_bits_desired; in set_qam_measurement()
6495 fec_rs_prescale = ext_attr->fec_rs_prescale; in set_qam_measurement()
6514 return -EINVAL; in set_qam_measurement()
6517 /* Parameters for Reed-Solomon Decoder */ in set_qam_measurement()
6520 /* result is within 32 bit arithmetic -> */ in set_qam_measurement()
6524 switch (ext_attr->standard) { in set_qam_measurement()
6533 return -EINVAL; in set_qam_measurement()
6536 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ in set_qam_measurement()
6540 return -EIO; in set_qam_measurement()
6543 if (ext_attr->standard != DRX_STANDARD_ITU_B) in set_qam_measurement()
6551 switch (ext_attr->standard) { in set_qam_measurement()
6566 return -EINVAL; in set_qam_measurement()
6570 return -EINVAL; in set_qam_measurement()
6588 ext_attr->fec_rs_period = (u16) fec_rs_period; in set_qam_measurement()
6589 ext_attr->fec_rs_prescale = fec_rs_prescale; in set_qam_measurement()
6606 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam_measurement()
6611 /* result is within 32 bit arithmetic -> */ in set_qam_measurement()
6615 fec_vd_plen = ext_attr->fec_vd_plen; in set_qam_measurement()
6616 qam_vd_prescale = ext_attr->qam_vd_prescale; in set_qam_measurement()
6633 return -EINVAL; in set_qam_measurement()
6637 return -EIO; in set_qam_measurement()
6657 ext_attr->qam_vd_period = (u16) qam_vd_period; in set_qam_measurement()
6658 ext_attr->qam_vd_prescale = qam_vd_prescale; in set_qam_measurement()
6676 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam16()
6773 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); in set_qam16()
6778 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); in set_qam16()
6783 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); in set_qam16()
6911 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam32()
6998 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); in set_qam32()
7003 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); in set_qam32()
7008 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); in set_qam32()
7013 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); in set_qam32()
7018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); in set_qam32()
7146 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam64()
7149 /* this is hw reset value. no necessary to re-write */ in set_qam64()
7244 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); in set_qam64()
7249 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); in set_qam64()
7254 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); in set_qam64()
7382 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam128()
7479 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); in set_qam128()
7489 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); in set_qam128()
7617 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam256()
7724 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); in set_qam256()
7876 DRXJ_16TO8(-1), /* re0 */ in set_qam()
7879 DRXJ_16TO8(-1), /* re3 */ in set_qam()
7880 DRXJ_16TO8(-1), /* re4 */ in set_qam()
7883 DRXJ_16TO8(-2), /* re7 */ in set_qam()
7886 DRXJ_16TO8(-1), /* re10 */ in set_qam()
7887 DRXJ_16TO8(-3), /* re11 */ in set_qam()
7890 DRXJ_16TO8(-8), /* re14 */ in set_qam()
7893 DRXJ_16TO8(-13), /* re17 */ in set_qam()
7894 DRXJ_16TO8(-19), /* re18 */ in set_qam()
7897 DRXJ_16TO8(-53), /* re21 */ in set_qam()
7898 DRXJ_16TO8(-31), /* re22 */ in set_qam()
7901 DRXJ_16TO8(-190), /* re25 */ in set_qam()
7902 DRXJ_16TO8(-40), /* re26 */ in set_qam()
7907 DRXJ_16TO8(-2), /* re1 */ in set_qam()
7910 DRXJ_16TO8(-2), /* re4 */ in set_qam()
7913 DRXJ_16TO8(-2), /* re7 */ in set_qam()
7914 DRXJ_16TO8(-4), /* re8 */ in set_qam()
7917 DRXJ_16TO8(-6), /* re11 */ in set_qam()
7920 DRXJ_16TO8(-5), /* re14 */ in set_qam()
7921 DRXJ_16TO8(-3), /* re15 */ in set_qam()
7923 DRXJ_16TO8(-4), /* re17 */ in set_qam()
7924 DRXJ_16TO8(-19), /* re18 */ in set_qam()
7927 DRXJ_16TO8(-45), /* re21 */ in set_qam()
7928 DRXJ_16TO8(-36), /* re22 */ in set_qam()
7931 DRXJ_16TO8(-185), /* re25 */ in set_qam()
7932 DRXJ_16TO8(-46), /* re26 */ in set_qam()
7936 DRXJ_16TO8(-2), /* re0 */ in set_qam()
7939 DRXJ_16TO8(-4), /* re3 */ in set_qam()
7942 DRXJ_16TO8(-2), /* re6 */ in set_qam()
7943 DRXJ_16TO8(-4), /* re7 */ in set_qam()
7946 DRXJ_16TO8(-8), /* re10 */ in set_qam()
7949 DRXJ_16TO8(-8), /* re13 */ in set_qam()
7950 DRXJ_16TO8(-15), /* re14 */ in set_qam()
7953 DRXJ_16TO8(-27), /* re17 */ in set_qam()
7954 DRXJ_16TO8(-22), /* re18 */ in set_qam()
7957 DRXJ_16TO8(-69), /* re21 */ in set_qam()
7958 DRXJ_16TO8(-28), /* re22 */ in set_qam()
7961 DRXJ_16TO8(-201), /* re25 */ in set_qam()
7962 DRXJ_16TO8(-32), /* re26 */ in set_qam()
7966 DRXJ_16TO8(-3), /* re0 */ in set_qam()
7969 DRXJ_16TO8(-4), /* re3 */ in set_qam()
7972 DRXJ_16TO8(-1), /* re6 */ in set_qam()
7973 DRXJ_16TO8(-4), /* re7 */ in set_qam()
7976 DRXJ_16TO8(-5), /* re10 */ in set_qam()
7979 DRXJ_16TO8(-4), /* re13 */ in set_qam()
7980 DRXJ_16TO8(-12), /* re14 */ in set_qam()
7983 DRXJ_16TO8(-21), /* re17 */ in set_qam()
7984 DRXJ_16TO8(-20), /* re18 */ in set_qam()
7987 DRXJ_16TO8(-62), /* re21 */ in set_qam()
7988 DRXJ_16TO8(-28), /* re22 */ in set_qam()
7991 DRXJ_16TO8(-197), /* re25 */ in set_qam()
7992 DRXJ_16TO8(-33), /* re26 */ in set_qam()
7996 dev_addr = demod->my_i2c_dev_addr; in set_qam()
7997 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam()
7998 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_qam()
8001 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8002 switch (channel->constellation) { in set_qam()
8007 channel->symbolrate = 5360537; in set_qam()
8013 channel->symbolrate = 5056941; in set_qam()
8017 return -EINVAL; in set_qam()
8020 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; in set_qam()
8021 if (channel->symbolrate == 0) { in set_qam()
8023 return -EIO; in set_qam()
8026 (adc_frequency / channel->symbolrate) * (1 << 21) + in set_qam()
8028 ((adc_frequency % channel->symbolrate), in set_qam()
8029 channel->symbolrate) >> 7) - (1 << 23); in set_qam()
8032 (channel->symbolrate + in set_qam()
8041 if (ext_attr->standard == DRX_STANDARD_ITU_A) { in set_qam()
8043 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8045 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8047 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8048 set_param_parameters[1] = channel->interleavemode; /* interleave mode */ in set_qam()
8049 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam()
8051 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8054 return -EINVAL; in set_qam()
8117 -set env in set_qam()
8118 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) in set_qam()
8149 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; in set_qam()
8150 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); in set_qam()
8159 /* TODO: remove re-writes of HW reset values */ in set_qam()
8183 if (!ext_attr->has_lna) { in set_qam()
8264 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8281 switch (channel->constellation) { in set_qam()
8320 return -EIO; in set_qam()
8470 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); in set_qam()
8475 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); in set_qam()
8485 qam_pga_cfg.gain = ext_attr->qam_pga_cfg; in set_qam()
8492 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); in set_qam()
8500 if (ext_attr->standard == DRX_STANDARD_ITU_A) { in set_qam()
8511 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8512 switch (channel->constellation) { in set_qam()
8538 return -EIO; in set_qam()
8540 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam()
8554 switch (channel->constellation) { in set_qam()
8591 return -EIO; in set_qam()
8623 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in set_qam()
8676 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam_flip_spec()
8677 struct drxj_data *ext_attr = demod->my_ext_attr; in qam_flip_spec()
8722 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs; in qam_flip_spec()
8724 iqm_fs_rate_ofs -= 2 * ofsofs; in qam_flip_spec()
8767 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; in qam_flip_spec()
8768 ext_attr->pos_image = (ext_attr->pos_image) ? false : true; in qam_flip_spec()
8795 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8808 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8871 struct drxj_data *ext_attr = demod->my_ext_attr; in qam64auto()
8872 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam64auto()
8873 struct drx39xxj_state *state = dev_addr->user_data; in qam64auto()
8874 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in qam64auto()
8901 if (p->cnr.stat[0].svalue > 20800) { in qam64auto()
8911 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam64auto()
8913 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8918 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8929 if (channel->mirror == DRX_MIRROR_AUTO) { in qam64auto()
8931 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8936 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); in qam64auto()
8942 ext_attr->mirror = DRX_MIRROR_YES; in qam64auto()
8956 jiffies_to_msecs(jiffies) - in qam64auto()
8957 DRXJ_QAM_MAX_WAITTIME - timeout_ofs; in qam64auto()
8963 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam64auto()
8970 if (p->cnr.stat[0].svalue > 20800) { in qam64auto()
8971 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8976 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8983 jiffies_to_msecs(jiffies) - in qam64auto()
8984 DRXJ_QAM_MAX_WAITTIME - timeout_ofs; in qam64auto()
8995 ((jiffies_to_msecs(jiffies) - start_time) < in qam64auto()
9019 struct drxj_data *ext_attr = demod->my_ext_attr; in qam256auto()
9020 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam256auto()
9021 struct drx39xxj_state *state = dev_addr->user_data; in qam256auto()
9022 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in qam256auto()
9047 if (p->cnr.stat[0].svalue > 26800) { in qam256auto()
9056 if ((channel->mirror == DRX_MIRROR_AUTO) && in qam256auto()
9057 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam256auto()
9059 ext_attr->mirror = DRX_MIRROR_YES; in qam256auto()
9068 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; in qam256auto()
9081 ((jiffies_to_msecs(jiffies) - start_time) < in qam256auto()
9106 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam_channel()
9109 switch (channel->constellation) { in set_qam_channel()
9113 return -EINVAL; in set_qam_channel()
9116 if (ext_attr->standard != DRX_STANDARD_ITU_B) in set_qam_channel()
9117 return -EINVAL; in set_qam_channel()
9119 ext_attr->constellation = channel->constellation; in set_qam_channel()
9120 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9121 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9123 ext_attr->mirror = channel->mirror; in set_qam_channel()
9131 if (channel->constellation == DRX_CONSTELLATION_QAM64) in set_qam_channel()
9143 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam_channel()
9149 channel->constellation = DRX_CONSTELLATION_QAM256; in set_qam_channel()
9150 ext_attr->constellation = DRX_CONSTELLATION_QAM256; in set_qam_channel()
9151 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9152 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9154 ext_attr->mirror = channel->mirror; in set_qam_channel()
9169 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9174 channel->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9175 ext_attr->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9176 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9177 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9179 ext_attr->mirror = channel->mirror; in set_qam_channel()
9181 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9188 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9195 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9209 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9224 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9225 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam_channel()
9228 channel->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9229 ext_attr->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9232 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9233 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9235 ext_attr->mirror = channel->mirror; in set_qam_channel()
9236 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9243 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9250 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9264 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9277 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9279 return -EINVAL; in set_qam_channel()
9283 return -EINVAL; in set_qam_channel()
9290 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9313 /* check arguments */ in get_qamrs_err_count()
9315 return -EINVAL; in get_qamrs_err_count()
9350 /* These register values are fetched in non-atomic fashion */ in get_qamrs_err_count()
9353 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M; in get_qamrs_err_count()
9354 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M; in get_qamrs_err_count()
9355 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M; in get_qamrs_err_count()
9356 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M; in get_qamrs_err_count()
9357 rs_errors->nr_snc_par_fail_count = in get_qamrs_err_count()
9371 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9374 * \retval -EINVAL sig_strength is NULL.
9375 * \retval -EIO Erroneous data, sig_strength contains invalid data.
9384 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in get_sig_strength()
9417 return -EIO; in get_sig_strength()
9420 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - in get_sig_strength()
9427 return -EIO; in get_sig_strength()
9430 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); in get_sig_strength()
9434 return -EIO; in get_sig_strength()
9454 * \retval -EINVAL sig_quality is NULL.
9455 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9457 * Pre-condition: Device must be started and in lock.
9462 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in ctrl_get_qam_sig_quality()
9463 struct drxj_data *ext_attr = demod->my_ext_attr; in ctrl_get_qam_sig_quality()
9464 struct drx39xxj_state *state = dev_addr->user_data; in ctrl_get_qam_sig_quality()
9465 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in ctrl_get_qam_sig_quality()
9467 enum drx_modulation constellation = ext_attr->constellation; in ctrl_get_qam_sig_quality()
9494 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9517 fec_rs_period = ext_attr->fec_rs_period; in ctrl_get_qam_sig_quality()
9518 fec_rs_prescale = ext_attr->fec_rs_prescale; in ctrl_get_qam_sig_quality()
9519 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen; in ctrl_get_qam_sig_quality()
9520 qam_vd_period = ext_attr->qam_vd_period; in ctrl_get_qam_sig_quality()
9521 qam_vd_prescale = ext_attr->qam_vd_prescale; in ctrl_get_qam_sig_quality()
9522 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen; in ctrl_get_qam_sig_quality()
9542 rc = -EIO; in ctrl_get_qam_sig_quality()
9546 /* ------------------------------ */ in ctrl_get_qam_sig_quality()
9548 /* ------------------------------ */ in ctrl_get_qam_sig_quality()
9555 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power); in ctrl_get_qam_sig_quality()
9557 /* ----------------------------------------- */ in ctrl_get_qam_sig_quality()
9559 /* ----------------------------------------- */ in ctrl_get_qam_sig_quality()
9579 qam_vd_ser = m << ((e > 2) ? (e - 3) : e); in ctrl_get_qam_sig_quality()
9581 /* --------------------------------------- */ in ctrl_get_qam_sig_quality()
9583 /* --------------------------------------- */ in ctrl_get_qam_sig_quality()
9584 /* pre RS BER is good if it is below 3.5e-4 */ in ctrl_get_qam_sig_quality()
9591 /* pre Reed-Solomon bit error count */ in ctrl_get_qam_sig_quality()
9625 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9626 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9627 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9628 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9629 p->block_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9630 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in ctrl_get_qam_sig_quality()
9632 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100; in ctrl_get_qam_sig_quality()
9633 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in ctrl_get_qam_sig_quality()
9634 p->pre_bit_error.stat[0].uvalue += qam_vd_ser; in ctrl_get_qam_sig_quality()
9635 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; in ctrl_get_qam_sig_quality()
9637 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber; in ctrl_get_qam_sig_quality()
9638 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e; in ctrl_get_qam_sig_quality()
9641 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber; in ctrl_get_qam_sig_quality()
9642 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e; in ctrl_get_qam_sig_quality()
9644 p->block_error.stat[0].uvalue += pkt_errs; in ctrl_get_qam_sig_quality()
9647 rc = get_acc_pkt_err(demod, &sig_quality->packet_error); in ctrl_get_qam_sig_quality()
9656 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9657 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9658 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9659 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9660 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9661 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9732 /* -------------------------------------------------------------------------- */
9748 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_atv()
9847 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; in power_down_aud()
9848 ext_attr = (struct drxj_data *) demod->my_ext_attr; in power_down_aud()
9856 ext_attr->aud_data.audio_is_active = false; in power_down_aud()
9872 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_orx_nsu_aox()
9914 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*s…
9915 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqr…
9916 …ne IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full rais…
9941 …{DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_… in ctrl_set_oob()
9942 …{DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B … in ctrl_set_oob()
9943 …{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B … in ctrl_set_oob()
9944 …{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B =… in ctrl_set_oob()
9948 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_oob()
9949 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_oob()
9950 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; in ctrl_set_oob()
9952 /* Check parameters */ in ctrl_set_oob()
9976 ext_attr->oob_power_on = false; in ctrl_set_oob()
9980 freq = oob_param->frequency; in ctrl_set_oob()
9982 return -EIO; in ctrl_set_oob()
9983 freq = (freq - 50000) / 50; in ctrl_set_oob()
9988 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; in ctrl_set_oob()
9990 index = (u16) ((freq - 400) / 200); in ctrl_set_oob()
9991 remainder = (u16) ((freq - 400) % 200); in ctrl_set_oob()
9993 trk_filtercfg[index] - (trk_filtercfg[index] - in ctrl_set_oob()
10037 /* 1-data rate;2-frequency */ in ctrl_set_oob()
10038 switch (oob_param->standard) { in ctrl_set_oob()
10042 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10047 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10060 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10065 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10079 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10084 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10152 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); in ctrl_set_oob()
10192 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ in ctrl_set_oob()
10198 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10208 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10219 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ in ctrl_set_oob()
10225 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10235 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10246 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ in ctrl_set_oob()
10252 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10262 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10273 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ in ctrl_set_oob()
10279 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10289 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10300 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ in ctrl_set_oob()
10306 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10316 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10327 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ in ctrl_set_oob()
10333 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10343 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); in ctrl_set_oob()
10354 /* PRE-Filter coefficients (PFI) */ in ctrl_set_oob()
10366 /* NYQUIST-Filter coefficients (NYQ) */ in ctrl_set_oob()
10408 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); in ctrl_set_oob()
10414 ext_attr->oob_power_on = true; in ctrl_set_oob()
10457 /*== check arguments ======================================================*/ in ctrl_set_channel()
10459 return -EINVAL; in ctrl_set_channel()
10461 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_channel()
10462 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_channel()
10463 standard = ext_attr->standard; in ctrl_set_channel()
10465 /* check valid standards */ in ctrl_set_channel()
10476 return -EINVAL; in ctrl_set_channel()
10479 /* check bandwidth QAM annex B, NTSC and 8VSB */ in ctrl_set_channel()
10483 switch (channel->bandwidth) { in ctrl_set_channel()
10486 channel->bandwidth = DRX_BANDWIDTH_6MHZ; in ctrl_set_channel()
10491 return -EINVAL; in ctrl_set_channel()
10496 -check symbolrate and constellation in ctrl_set_channel()
10497 -derive bandwidth from symbolrate (input bandwidth is ignored) in ctrl_set_channel()
10515 if (channel->symbolrate < min_symbol_rate || in ctrl_set_channel()
10516 channel->symbolrate > max_symbol_rate) { in ctrl_set_channel()
10517 return -EINVAL; in ctrl_set_channel()
10520 switch (channel->constellation) { in ctrl_set_channel()
10526 bandwidth_temp = channel->symbolrate * bw_rolloff_factor; in ctrl_set_channel()
10533 channel->bandwidth = DRX_BANDWIDTH_6MHZ; in ctrl_set_channel()
10536 channel->bandwidth = DRX_BANDWIDTH_7MHZ; in ctrl_set_channel()
10538 channel->bandwidth = DRX_BANDWIDTH_8MHZ; in ctrl_set_channel()
10542 return -EINVAL; in ctrl_set_channel()
10547 -check constellation in ctrl_set_channel()
10550 switch (channel->constellation) { in ctrl_set_channel()
10556 return -EINVAL; in ctrl_set_channel()
10559 switch (channel->interleavemode) { in ctrl_set_channel()
10581 return -EINVAL; in ctrl_set_channel()
10585 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { in ctrl_set_channel()
10589 switch (channel->bandwidth) { in ctrl_set_channel()
10601 return -EINVAL; in ctrl_set_channel()
10622 if (channel->mirror == DRX_MIRROR_AUTO) in ctrl_set_channel()
10623 ext_attr->mirror = DRX_MIRROR_NO; in ctrl_set_channel()
10625 ext_attr->mirror = channel->mirror; in ctrl_set_channel()
10650 return -EIO; in ctrl_set_channel()
10654 ext_attr->reset_pkt_err_acc = true; in ctrl_set_channel()
10672 * \retval -EINVAL sig_quality is NULL.
10673 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10680 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in ctrl_sig_quality()
10681 struct drxj_data *ext_attr = demod->my_ext_attr; in ctrl_sig_quality()
10682 struct drx39xxj_state *state = dev_addr->user_data; in ctrl_sig_quality()
10683 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in ctrl_sig_quality()
10684 enum drx_standard standard = ext_attr->standard; in ctrl_sig_quality()
10692 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10694 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in ctrl_sig_quality()
10695 p->strength.stat[0].uvalue = 65535UL * strength/ 100; in ctrl_sig_quality()
10708 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10709 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10710 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10711 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10712 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10713 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10714 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10719 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10721 p->block_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10722 p->block_error.stat[0].uvalue += err; in ctrl_sig_quality()
10723 p->block_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10724 p->block_count.stat[0].uvalue += pkt; in ctrl_sig_quality()
10727 /* PostViterbi is compute in steps of 10^(-6) */ in ctrl_sig_quality()
10730 pr_err("error %d getting pre-ber\n", rc); in ctrl_sig_quality()
10731 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10733 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10734 p->pre_bit_error.stat[0].uvalue += ber; in ctrl_sig_quality()
10735 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10736 p->pre_bit_count.stat[0].uvalue += cnt; in ctrl_sig_quality()
10741 pr_err("error %d getting post-ber\n", rc); in ctrl_sig_quality()
10742 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10744 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10745 p->post_bit_error.stat[0].uvalue += ber; in ctrl_sig_quality()
10746 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10747 p->post_bit_count.stat[0].uvalue += cnt; in ctrl_sig_quality()
10752 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10754 p->cnr.stat[0].svalue = mer * 100; in ctrl_sig_quality()
10755 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in ctrl_sig_quality()
10771 return -EIO; in ctrl_sig_quality()
10805 /* check arguments */ in ctrl_lock_status()
10807 return -EINVAL; in ctrl_lock_status()
10809 dev_addr = demod->my_i2c_dev_addr; in ctrl_lock_status()
10810 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_lock_status()
10811 standard = ext_attr->standard; in ctrl_lock_status()
10832 return -EIO; in ctrl_lock_status()
10886 /* check arguments */ in ctrl_set_standard()
10888 return -EINVAL; in ctrl_set_standard()
10890 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_standard()
10891 prev_standard = ext_attr->standard; in ctrl_set_standard()
10920 rc = -EINVAL; in ctrl_set_standard()
10928 ext_attr->standard = *standard; in ctrl_set_standard()
10937 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); in ctrl_set_standard()
10953 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_set_standard()
10954 return -EINVAL; in ctrl_set_standard()
10960 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_set_standard()
10969 if (ext_attr->has_lna) { in drxj_reset_mode()
10972 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
10973 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; in drxj_reset_mode()
10974 ext_attr->qam_pga_cfg = 140 + (11 * 13); in drxj_reset_mode()
10976 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
10977 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; in drxj_reset_mode()
10978 ext_attr->vsb_pga_cfg = 140 + (11 * 13); in drxj_reset_mode()
10982 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
10983 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
10984 ext_attr->qam_if_agc_cfg.min_output_level = 0; in drxj_reset_mode()
10985 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
10986 ext_attr->qam_if_agc_cfg.speed = 3; in drxj_reset_mode()
10987 ext_attr->qam_if_agc_cfg.top = 1297; in drxj_reset_mode()
10988 ext_attr->qam_pga_cfg = 140; in drxj_reset_mode()
10990 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
10991 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
10992 ext_attr->vsb_if_agc_cfg.min_output_level = 0; in drxj_reset_mode()
10993 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
10994 ext_attr->vsb_if_agc_cfg.speed = 3; in drxj_reset_mode()
10995 ext_attr->vsb_if_agc_cfg.top = 1024; in drxj_reset_mode()
10996 ext_attr->vsb_pga_cfg = 140; in drxj_reset_mode()
11001 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
11002 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
11003 ext_attr->qam_rf_agc_cfg.min_output_level = 0; in drxj_reset_mode()
11004 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
11005 ext_attr->qam_rf_agc_cfg.speed = 3; in drxj_reset_mode()
11006 ext_attr->qam_rf_agc_cfg.top = 9500; in drxj_reset_mode()
11007 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; in drxj_reset_mode()
11008 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
11009 ext_attr->qam_pre_saw_cfg.reference = 0x07; in drxj_reset_mode()
11010 ext_attr->qam_pre_saw_cfg.use_pre_saw = true; in drxj_reset_mode()
11013 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
11014 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
11015 ext_attr->vsb_rf_agc_cfg.min_output_level = 0; in drxj_reset_mode()
11016 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
11017 ext_attr->vsb_rf_agc_cfg.speed = 3; in drxj_reset_mode()
11018 ext_attr->vsb_rf_agc_cfg.top = 9500; in drxj_reset_mode()
11019 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; in drxj_reset_mode()
11020 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
11021 ext_attr->vsb_pre_saw_cfg.reference = 0x07; in drxj_reset_mode()
11022 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; in drxj_reset_mode()
11032 * \retval -EIO I2C error or other failure
11033 * \retval -EINVAL Invalid mode argument.
11046 common_attr = (struct drx_common_attr *) demod->my_common_attr; in ctrl_power_mode()
11047 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_power_mode()
11048 dev_addr = demod->my_i2c_dev_addr; in ctrl_power_mode()
11050 /* Check arguments */ in ctrl_power_mode()
11052 return -EINVAL; in ctrl_power_mode()
11055 if (common_attr->current_power_mode == *mode) in ctrl_power_mode()
11074 return -EINVAL; in ctrl_power_mode()
11077 /* Check if device needs to be powered up */ in ctrl_power_mode()
11078 if ((common_attr->current_power_mode != DRX_POWER_UP)) { in ctrl_power_mode()
11094 /* Set pins with possible pull-ups connected to them in input mode */ in ctrl_power_mode()
11103 switch (ext_attr->standard) { in ctrl_power_mode()
11127 rc = power_down_atv(demod, ext_attr->standard, true); in ctrl_power_mode()
11138 return -EIO; in ctrl_power_mode()
11140 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_power_mode()
11163 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in ctrl_power_mode()
11172 common_attr->current_power_mode = *mode; in ctrl_power_mode()
11185 * \brief Set Pre-saw reference.
11190 * Check arguments
11201 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_pre_saw()
11202 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_pre_saw()
11204 /* check arguments */ in ctrl_set_cfg_pre_saw()
11205 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) in ctrl_set_cfg_pre_saw()
11207 return -EINVAL; in ctrl_set_cfg_pre_saw()
11211 if ((ext_attr->standard == pre_saw->standard) || in ctrl_set_cfg_pre_saw()
11212 (DRXJ_ISQAMSTD(ext_attr->standard) && in ctrl_set_cfg_pre_saw()
11213 DRXJ_ISQAMSTD(pre_saw->standard)) || in ctrl_set_cfg_pre_saw()
11214 (DRXJ_ISATVSTD(ext_attr->standard) && in ctrl_set_cfg_pre_saw()
11215 DRXJ_ISATVSTD(pre_saw->standard))) { in ctrl_set_cfg_pre_saw()
11216 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); in ctrl_set_cfg_pre_saw()
11223 /* Store pre-saw settings */ in ctrl_set_cfg_pre_saw()
11224 switch (pre_saw->standard) { in ctrl_set_cfg_pre_saw()
11226 ext_attr->vsb_pre_saw_cfg = *pre_saw; in ctrl_set_cfg_pre_saw()
11232 ext_attr->qam_pre_saw_cfg = *pre_saw; in ctrl_set_cfg_pre_saw()
11236 return -EINVAL; in ctrl_set_cfg_pre_saw()
11253 * Check arguments
11265 /* check arguments */ in ctrl_set_cfg_afe_gain()
11267 return -EINVAL; in ctrl_set_cfg_afe_gain()
11269 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_afe_gain()
11270 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_afe_gain()
11272 switch (afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11282 return -EINVAL; in ctrl_set_cfg_afe_gain()
11288 if (afe_gain->gain >= 329) in ctrl_set_cfg_afe_gain()
11290 else if (afe_gain->gain <= 147) in ctrl_set_cfg_afe_gain()
11293 gain = (afe_gain->gain - 140 + 6) / 13; in ctrl_set_cfg_afe_gain()
11296 if (ext_attr->standard == afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11305 switch (afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11307 ext_attr->vsb_pga_cfg = gain * 13 + 140; in ctrl_set_cfg_afe_gain()
11313 ext_attr->qam_pga_cfg = gain * 13 + 140; in ctrl_set_cfg_afe_gain()
11317 return -EIO; in ctrl_set_cfg_afe_gain()
11359 (demod->my_common_attr == NULL) || in drxj_open()
11360 (demod->my_ext_attr == NULL) || in drxj_open()
11361 (demod->my_i2c_dev_addr == NULL) || in drxj_open()
11362 (demod->my_common_attr->is_opened)) { in drxj_open()
11363 return -EINVAL; in drxj_open()
11366 /* Check arguments */ in drxj_open()
11367 if (demod->my_ext_attr == NULL) in drxj_open()
11368 return -EINVAL; in drxj_open()
11370 dev_addr = demod->my_i2c_dev_addr; in drxj_open()
11371 ext_attr = (struct drxj_data *) demod->my_ext_attr; in drxj_open()
11372 common_attr = (struct drx_common_attr *) demod->my_common_attr; in drxj_open()
11380 rc = -EINVAL; in drxj_open()
11393 * Soft reset of sys- and osc-clockdomain in drxj_open()
11397 * Btw, this is coherent with DRX-K, where we send reset codes in drxj_open()
11398 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains. in drxj_open()
11438 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in drxj_open()
11460 if (common_attr->microcode_file != NULL) { in drxj_open()
11463 common_attr->is_opened = true; in drxj_open()
11464 ucode_info.mc_file = common_attr->microcode_file; in drxj_open()
11466 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) { in drxj_open()
11468 rc = -EINVAL; in drxj_open()
11477 if (common_attr->verify_microcode == true) { in drxj_open()
11485 common_attr->is_opened = false; in drxj_open()
11496 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; in drxj_open()
11497 common_attr->scan_desired_lock = DRX_LOCKED; in drxj_open()
11500 ext_attr->standard = DRX_STANDARD_UNKNOWN; in drxj_open()
11545 ext_attr->aud_data = drxj_default_aud_data_g; in drxj_open()
11547 demod->my_common_attr->is_opened = true; in drxj_open()
11551 common_attr->is_opened = false; in drxj_open()
11564 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in drxj_close()
11568 if ((demod->my_common_attr == NULL) || in drxj_close()
11569 (demod->my_ext_attr == NULL) || in drxj_close()
11570 (demod->my_i2c_dev_addr == NULL) || in drxj_close()
11571 (!demod->my_common_attr->is_opened)) { in drxj_close()
11572 return -EINVAL; in drxj_close()
11608 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
11636 * drx_check_firmware - checks if the loaded firmware is valid
11653 * and firmware check in drx_check_firmware()
11689 /* Aux block. Check type */ in drx_check_firmware()
11718 return -EINVAL; in drx_check_firmware()
11722 * drx_ctrl_u_code - Handle microcode upload or verify.
11729 * - In case of UCODE_UPLOAD: code is successfully uploaded.
11730 * - In case of UCODE_VERIFY: image on device is equal to
11732 * -EIO:
11733 * - In case of UCODE_UPLOAD: I2C error.
11734 * - In case of UCODE_VERIFY: I2C error or image on device
11736 * -EINVAL:
11737 * - Invalid arguments.
11738 * - Provided image is corrupt
11744 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in drx_ctrl_u_code()
11754 /* Check arguments */ in drx_ctrl_u_code()
11755 if (!mc_info || !mc_info->mc_file) in drx_ctrl_u_code()
11756 return -EINVAL; in drx_ctrl_u_code()
11758 mc_file = mc_info->mc_file; in drx_ctrl_u_code()
11760 if (!demod->firmware) { in drx_ctrl_u_code()
11763 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); in drx_ctrl_u_code()
11768 demod->firmware = fw; in drx_ctrl_u_code()
11770 if (demod->firmware->size < 2 * sizeof(u16)) { in drx_ctrl_u_code()
11771 rc = -EINVAL; in drx_ctrl_u_code()
11777 mc_file, demod->firmware->size); in drx_ctrl_u_code()
11780 mc_data_init = demod->firmware->data; in drx_ctrl_u_code()
11781 size = demod->firmware->size; in drx_ctrl_u_code()
11784 /* Check data */ in drx_ctrl_u_code()
11791 rc = -EINVAL; in drx_ctrl_u_code()
11821 (mc_data - mc_data_init), block_hdr.addr, in drx_ctrl_u_code()
11824 /* Check block header on: in drx_ctrl_u_code()
11825 - data larger than 64Kb in drx_ctrl_u_code()
11826 - if CRC enabled check CRC in drx_ctrl_u_code()
11833 rc = -EINVAL; in drx_ctrl_u_code()
11850 rc = -EIO; in drx_ctrl_u_code()
11852 mc_data - mc_data_init); in drx_ctrl_u_code()
11876 mc_data - mc_data_init); in drx_ctrl_u_code()
11877 return -EIO; in drx_ctrl_u_code()
11885 mc_data - mc_data_init); in drx_ctrl_u_code()
11886 return -EIO; in drx_ctrl_u_code()
11891 bytes_left -=((u32) bytes_to_comp); in drx_ctrl_u_code()
11896 return -EINVAL; in drx_ctrl_u_code()
11905 release_firmware(demod->firmware); in drx_ctrl_u_code()
11906 demod->firmware = NULL; in drx_ctrl_u_code()
11911 /* caller is expected to check if lna is supported before enabling */
11920 /* Configure user-I/O #3: enable read/write */ in drxj_set_lna_state()
11946 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_powerstate()
11947 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_powerstate()
11967 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_read_status()
11968 struct drx_demod_instance *demod = state->demod; in drx39xxj_read_status()
12015 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_ber()
12017 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_ber()
12022 if (!p->pre_bit_count.stat[0].uvalue) { in drx39xxj_read_ber()
12023 if (!p->pre_bit_error.stat[0].uvalue) in drx39xxj_read_ber()
12028 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue, in drx39xxj_read_ber()
12029 p->pre_bit_count.stat[0].uvalue); in drx39xxj_read_ber()
12037 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_signal_strength()
12039 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_signal_strength()
12044 *strength = p->strength.stat[0].uvalue; in drx39xxj_read_signal_strength()
12050 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_snr()
12053 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_snr()
12058 tmp64 = p->cnr.stat[0].svalue; in drx39xxj_read_snr()
12066 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_ucblocks()
12068 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_ucblocks()
12073 *ucb = p->block_error.stat[0].uvalue; in drx39xxj_read_ucblocks()
12082 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_set_frontend()
12083 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_frontend()
12084 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_frontend()
12110 if (fe->ops.tuner_ops.set_params) { in drx39xxj_set_frontend()
12113 if (fe->ops.i2c_gate_ctrl) in drx39xxj_set_frontend()
12114 fe->ops.i2c_gate_ctrl(fe, 1); in drx39xxj_set_frontend()
12117 fe->ops.tuner_ops.set_params(fe); in drx39xxj_set_frontend()
12120 if (fe->ops.tuner_ops.get_if_frequency) { in drx39xxj_set_frontend()
12121 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq); in drx39xxj_set_frontend()
12122 demod->my_common_attr->intermediate_freq = int_freq / 1000; in drx39xxj_set_frontend()
12125 if (fe->ops.i2c_gate_ctrl) in drx39xxj_set_frontend()
12126 fe->ops.i2c_gate_ctrl(fe, 0); in drx39xxj_set_frontend()
12129 switch (p->delivery_system) { in drx39xxj_set_frontend()
12136 switch (p->modulation) { in drx39xxj_set_frontend()
12149 return -EINVAL; in drx39xxj_set_frontend()
12156 return -EINVAL; in drx39xxj_set_frontend()
12161 channel.frequency = p->frequency / 1000; in drx39xxj_set_frontend()
12169 return -EINVAL; in drx39xxj_set_frontend()
12175 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drx39xxj_set_frontend()
12182 /* power-down the demodulator */ in drx39xxj_sleep()
12188 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_i2c_gate_ctrl()
12189 struct drx_demod_instance *demod = state->demod; in drx39xxj_i2c_gate_ctrl()
12195 state->i2c_gate_open); in drx39xxj_i2c_gate_ctrl()
12203 if (state->i2c_gate_open == enable) { in drx39xxj_i2c_gate_ctrl()
12214 state->i2c_gate_open = enable; in drx39xxj_i2c_gate_ctrl()
12221 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_init()
12222 struct drx_demod_instance *demod = state->demod; in drx39xxj_init()
12225 if (fe->exit == DVB_FE_DEVICE_RESUME) { in drx39xxj_init()
12227 demod->my_common_attr->is_opened = false; in drx39xxj_init()
12239 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in drx39xxj_set_lna()
12240 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_lna()
12241 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_lna()
12242 struct drxj_data *ext_attr = demod->my_ext_attr; in drx39xxj_set_lna()
12244 if (c->lna) { in drx39xxj_set_lna()
12245 if (!ext_attr->has_lna) { in drx39xxj_set_lna()
12247 return -EINVAL; in drx39xxj_set_lna()
12252 return drxj_set_lna_state(demod, c->lna); in drx39xxj_set_lna()
12258 tune->min_delay_ms = 1000; in drx39xxj_get_tune_settings()
12264 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_release()
12265 struct drx_demod_instance *demod = state->demod; in drx39xxj_release()
12268 if (fe->exit != DVB_FE_DEVICE_REMOVED) in drx39xxj_release()
12271 kfree(demod->my_ext_attr); in drx39xxj_release()
12272 kfree(demod->my_common_attr); in drx39xxj_release()
12273 kfree(demod->my_i2c_dev_addr); in drx39xxj_release()
12274 release_firmware(demod->firmware); in drx39xxj_release()
12317 state->i2c = i2c; in drx39xxj_attach()
12318 state->demod = demod; in drx39xxj_attach()
12321 demod->my_i2c_dev_addr = demod_addr; in drx39xxj_attach()
12322 demod->my_common_attr = demod_comm_attr; in drx39xxj_attach()
12323 demod->my_i2c_dev_addr->user_data = state; in drx39xxj_attach()
12324 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; in drx39xxj_attach()
12325 demod->my_common_attr->verify_microcode = true; in drx39xxj_attach()
12326 demod->my_common_attr->intermediate_freq = 5000; in drx39xxj_attach()
12327 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN; in drx39xxj_attach()
12328 demod->my_ext_attr = demod_ext_attr; in drx39xxj_attach()
12329 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; in drx39xxj_attach()
12330 demod->i2c = i2c; in drx39xxj_attach()
12339 memcpy(&state->frontend.ops, &drx39xxj_ops, in drx39xxj_attach()
12342 state->frontend.demodulator_priv = state; in drx39xxj_attach()
12344 /* Initialize stats - needed for DVBv5 stats to work */ in drx39xxj_attach()
12345 p = &state->frontend.dtv_property_cache; in drx39xxj_attach()
12346 p->strength.len = 1; in drx39xxj_attach()
12347 p->pre_bit_count.len = 1; in drx39xxj_attach()
12348 p->pre_bit_error.len = 1; in drx39xxj_attach()
12349 p->post_bit_count.len = 1; in drx39xxj_attach()
12350 p->post_bit_error.len = 1; in drx39xxj_attach()
12351 p->block_count.len = 1; in drx39xxj_attach()
12352 p->block_error.len = 1; in drx39xxj_attach()
12353 p->cnr.len = 1; in drx39xxj_attach()
12355 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drx39xxj_attach()
12356 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12357 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12358 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12359 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12360 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12361 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12362 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12364 return &state->frontend; in drx39xxj_attach()