Lines Matching refs:dib8000_write_word
251 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) in dib8000_write_word() function
403 dib8000_write_word(state, 298, nud); in dib8000_set_acquisition_mode()
458 dib8000_write_word(state, 299, smo_mode); in dib8000_set_output_mode()
459 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */ in dib8000_set_output_mode()
460 dib8000_write_word(state, 1286, outreg); in dib8000_set_output_mode()
461 dib8000_write_word(state, 1291, sram); in dib8000_set_output_mode()
473 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1 in dib8000_set_diversity_in()
474 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2 in dib8000_set_diversity_in()
476 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0 in dib8000_set_diversity_in()
477 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0 in dib8000_set_diversity_in()
483 dib8000_write_word(state, 270, 1); in dib8000_set_diversity_in()
484 dib8000_write_word(state, 271, 0); in dib8000_set_diversity_in()
487 dib8000_write_word(state, 270, 6); in dib8000_set_diversity_in()
488 dib8000_write_word(state, 271, 6); in dib8000_set_diversity_in()
491 dib8000_write_word(state, 270, 0); in dib8000_set_diversity_in()
492 dib8000_write_word(state, 271, 1); in dib8000_set_diversity_in()
498 dib8000_write_word(state, 903, tmp & ~(1 << 3)); in dib8000_set_diversity_in()
500 dib8000_write_word(state, 903, tmp | (1 << 3)); in dib8000_set_diversity_in()
539 dib8000_write_word(state, 774, reg_774); in dib8000_set_power_mode()
540 dib8000_write_word(state, 775, reg_775); in dib8000_set_power_mode()
541 dib8000_write_word(state, 776, reg_776); in dib8000_set_power_mode()
542 dib8000_write_word(state, 900, reg_900); in dib8000_set_power_mode()
543 dib8000_write_word(state, 1280, reg_1280); in dib8000_set_power_mode()
556 ret |= dib8000_write_word(state, 908, reg_908); in dib8000_set_adc_state()
561 dib8000_write_word(state, 1925, reg | in dib8000_set_adc_state()
568 dib8000_write_word(state, 1925, reg & ~(1<<4)); in dib8000_set_adc_state()
574 dib8000_write_word(state, 921, reg | (1 << 14) in dib8000_set_adc_state()
583 dib8000_write_word(state, 1925, in dib8000_set_adc_state()
611 ret |= dib8000_write_word(state, 907, reg_907); in dib8000_set_adc_state()
612 ret |= dib8000_write_word(state, 908, reg_908); in dib8000_set_adc_state()
633 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff)); in dib8000_set_bandwidth()
634 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff)); in dib8000_set_bandwidth()
644 dib8000_write_word(state, 922, (sad_sel << 2)); in dib8000_sad_calib()
645 dib8000_write_word(state, 923, 2048); in dib8000_sad_calib()
647 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1); in dib8000_sad_calib()
648 dib8000_write_word(state, 922, (sad_sel << 2)); in dib8000_sad_calib()
651 dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); in dib8000_sad_calib()
652 dib8000_write_word(state, 924, 776); in dib8000_sad_calib()
655 dib8000_write_word(state, 923, (1 << 0)); in dib8000_sad_calib()
656 dib8000_write_word(state, 923, (0 << 0)); in dib8000_sad_calib()
669 return dib8000_write_word(state, 106, value); in dib8000_set_wbd_ref()
676 dib8000_write_word(state, 23, in dib8000_reset_pll_common()
678 dib8000_write_word(state, 24, in dib8000_reset_pll_common()
681 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
682 dib8000_write_word(state, 24, in dib8000_reset_pll_common()
685 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); in dib8000_reset_pll_common()
686 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); in dib8000_reset_pll_common()
687 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); in dib8000_reset_pll_common()
690 dib8000_write_word(state, 922, bw->sad_cfg); in dib8000_reset_pll_common()
699 dib8000_write_word(state, 901, in dib8000_reset_pll()
707 dib8000_write_word(state, 902, clk_cfg1); in dib8000_reset_pll()
709 dib8000_write_word(state, 902, clk_cfg1); in dib8000_reset_pll()
715 dib8000_write_word(state, 904, in dib8000_reset_pll()
720 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | in dib8000_reset_pll()
725 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | in dib8000_reset_pll()
729 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) | in dib8000_reset_pll()
734 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); in dib8000_reset_pll()
737 dib8000_write_word(state, 1858, reg | 1); in dib8000_reset_pll()
739 dib8000_write_word(state, 904, (pll->modulo << 8)); in dib8000_reset_pll()
766 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15)); in dib8000_update_pll()
768 dib8000_write_word(state, 1856, reg_1856 | in dib8000_update_pll()
780 dib8000_write_word(state, 23, in dib8000_update_pll()
782 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff)); in dib8000_update_pll()
784 dib8000_write_word(state, 1857, reg_1857 | (1 << 15)); in dib8000_update_pll()
803 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */ in dib8000_update_pll()
805 dib8000_write_word(state, 898, 0x0004); /* sad */ in dib8000_update_pll()
815 …dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL … in dib8000_update_pll()
825 dib8000_write_word(st, 1029, st->cfg.gpio_dir); in dib8000_reset_gpio()
826 dib8000_write_word(st, 1030, st->cfg.gpio_val); in dib8000_reset_gpio()
830 dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos); in dib8000_reset_gpio()
832 dib8000_write_word(st, 1037, st->cfg.pwm_freq_div); in dib8000_reset_gpio()
841 dib8000_write_word(st, 1029, st->cfg.gpio_dir); in dib8000_cfg_gpio()
846 dib8000_write_word(st, 1030, st->cfg.gpio_val); in dib8000_cfg_gpio()
1041 dib8000_write_word(state, 1287, 0x0003); in dib8000_reset()
1054 dib8000_write_word(state, 770, 0xffff); in dib8000_reset()
1055 dib8000_write_word(state, 771, 0xffff); in dib8000_reset()
1056 dib8000_write_word(state, 772, 0xfffc); in dib8000_reset()
1057 dib8000_write_word(state, 898, 0x000c); /* restart sad */ in dib8000_reset()
1059 dib8000_write_word(state, 1280, 0x0045); in dib8000_reset()
1061 dib8000_write_word(state, 1280, 0x004d); in dib8000_reset()
1062 dib8000_write_word(state, 1281, 0x000c); in dib8000_reset()
1064 dib8000_write_word(state, 770, 0x0000); in dib8000_reset()
1065 dib8000_write_word(state, 771, 0x0000); in dib8000_reset()
1066 dib8000_write_word(state, 772, 0x0000); in dib8000_reset()
1067 dib8000_write_word(state, 898, 0x0004); // sad in dib8000_reset()
1068 dib8000_write_word(state, 1280, 0x0000); in dib8000_reset()
1069 dib8000_write_word(state, 1281, 0x0000); in dib8000_reset()
1074 dib8000_write_word(state, 906, state->cfg.drives); in dib8000_reset()
1078 dib8000_write_word(state, 906, 0x2d98); in dib8000_reset()
1084 dib8000_write_word(state, 898, 0x0004); in dib8000_reset()
1098 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */ in dib8000_reset()
1100 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */ in dib8000_reset()
1110 dib8000_write_word(state, r, *n++); in dib8000_reset()
1121 dib8000_write_word(state, 903, state->cfg.div_cfg); in dib8000_reset()
1124 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); in dib8000_reset()
1134 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); in dib8000_reset()
1146 dib8000_write_word(state, 770, 0x0a00); in dib8000_restart_agc()
1147 dib8000_write_word(state, 770, 0x0000); in dib8000_restart_agc()
1190 dib8000_write_word(state, 76, agc->setup); in dib8000_set_agc_config()
1191 dib8000_write_word(state, 77, agc->inv_gain); in dib8000_set_agc_config()
1192 dib8000_write_word(state, 78, agc->time_stabiliz); in dib8000_set_agc_config()
1193 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock); in dib8000_set_agc_config()
1196 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp); in dib8000_set_agc_config()
1197 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp); in dib8000_set_agc_config()
1204 dib8000_write_word(state, 106, state->wbd_ref); in dib8000_set_agc_config()
1206 dib8000_write_word(state, 106, agc->wbd_ref); in dib8000_set_agc_config()
1210 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2)); in dib8000_set_agc_config()
1213 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); in dib8000_set_agc_config()
1214 dib8000_write_word(state, 108, agc->agc1_max); in dib8000_set_agc_config()
1215 dib8000_write_word(state, 109, agc->agc1_min); in dib8000_set_agc_config()
1216 dib8000_write_word(state, 110, agc->agc2_max); in dib8000_set_agc_config()
1217 dib8000_write_word(state, 111, agc->agc2_min); in dib8000_set_agc_config()
1218 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2); in dib8000_set_agc_config()
1219 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib8000_set_agc_config()
1220 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib8000_set_agc_config()
1221 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib8000_set_agc_config()
1223 dib8000_write_word(state, 75, agc->agc1_pt3); in dib8000_set_agc_config()
1225 dib8000_write_word(state, 923, in dib8000_set_agc_config()
1261 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); in dib8000_agc_soft_split()
1283 dib8000_write_word(state, 1946, in dib8000_agc_startup()
1286 dib8000_write_word(state, 1947, reg | (1<<14) | in dib8000_agc_startup()
1291 dib8000_write_word(state, 1920, (reg | 0x3) & in dib8000_agc_startup()
1354 dib8000_write_word(state, 1798, reg); in dib8096p_host_bus_drive()
1359 dib8000_write_word(state, 1799, reg); in dib8096p_host_bus_drive()
1365 dib8000_write_word(state, 1800, reg); in dib8096p_host_bus_drive()
1370 dib8000_write_word(state, 1801, reg); in dib8096p_host_bus_drive()
1376 dib8000_write_word(state, 1802, reg); in dib8096p_host_bus_drive()
1404 dib8000_write_word(state, 1615, 1); in dib8096p_cfg_DibTx()
1405 dib8000_write_word(state, 1603, P_Kin); in dib8096p_cfg_DibTx()
1406 dib8000_write_word(state, 1605, P_Kout); in dib8096p_cfg_DibTx()
1407 dib8000_write_word(state, 1606, insertExtSynchro); in dib8096p_cfg_DibTx()
1408 dib8000_write_word(state, 1608, synchroMode); in dib8096p_cfg_DibTx()
1409 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff); in dib8096p_cfg_DibTx()
1410 dib8000_write_word(state, 1610, syncWord & 0xffff); in dib8096p_cfg_DibTx()
1411 dib8000_write_word(state, 1612, syncSize); in dib8096p_cfg_DibTx()
1412 dib8000_write_word(state, 1615, 0); in dib8096p_cfg_DibTx()
1426 dib8000_write_word(state, 1542, syncFreq); in dib8096p_cfg_DibRx()
1429 dib8000_write_word(state, 1554, 1); in dib8096p_cfg_DibRx()
1430 dib8000_write_word(state, 1536, P_Kin); in dib8096p_cfg_DibRx()
1431 dib8000_write_word(state, 1537, P_Kout); in dib8096p_cfg_DibRx()
1432 dib8000_write_word(state, 1539, synchroMode); in dib8096p_cfg_DibRx()
1433 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff); in dib8096p_cfg_DibRx()
1434 dib8000_write_word(state, 1541, syncWord & 0xffff); in dib8096p_cfg_DibRx()
1435 dib8000_write_word(state, 1543, syncSize); in dib8096p_cfg_DibRx()
1436 dib8000_write_word(state, 1544, dataOutRate); in dib8096p_cfg_DibRx()
1437 dib8000_write_word(state, 1554, 0); in dib8096p_cfg_DibRx()
1455 dib8000_write_word(state, 1287, reg_1287); in dib8096p_enMpegMux()
1473 dib8000_write_word(state, 1287, reg_1287); in dib8096p_configMpegMux()
1498 dib8000_write_word(state, 1288, reg_1288); in dib8096p_setDibTxMux()
1523 dib8000_write_word(state, 1288, reg_1288); in dib8096p_setHostBusMux()
1545 dib8000_write_word(state, 1287, reg_1287); in dib8096p_set_diversity_in()
1644 ret |= dib8000_write_word(state, 299, smo_mode); in dib8096p_set_output_mode()
1646 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold); in dib8096p_set_output_mode()
1647 ret |= dib8000_write_word(state, 1286, outreg); in dib8096p_set_output_mode()
1687 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); in dib8096p_tuner_write_serpar()
1688 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); in dib8096p_tuner_write_serpar()
1708 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f)); in dib8096p_tuner_read_serpar()
1744 dib8000_write_word(state, apb_address, in dib8096p_rw_on_apb()
1862 dib8000_write_word(state, 921, word); in dib8096p_tuner_xfer()
1911 dib8000_write_word(state, 1922, en_cur_state); in dib8096p_tuner_sleep()
1963 dib8000_write_word(state, 29, (u16) (timf >> 16)); in dib8000_update_timf()
1964 dib8000_write_word(state, 30, (u16) (timf & 0xffff)); in dib8000_update_timf()
2037 …dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment… in dib8000_set_layer()
2080 dib8000_write_word(state, 215 + i, adp[i]); in dib8000_adp_fine_tune()
2089 dib8000_write_word(state, 116, ana_gain); in dib8000_update_ana_gain()
2094 dib8000_write_word(state, 80 + i, adc_target_16dB[i]); in dib8000_update_ana_gain()
2097 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355); in dib8000_update_ana_gain()
2107 dib8000_write_word(state, 117 + mode, ana_fe[mode]); in dib8000_load_ana_fe_coefs()
2170 dib8000_write_word(state, 180, (16 << 6) | 9); in dib8000_set_13seg_channel()
2171 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2); in dib8000_set_13seg_channel()
2174 dib8000_write_word(state, 181+i, coff_pow); in dib8000_set_13seg_channel()
2178 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1); in dib8000_set_13seg_channel()
2181 dib8000_write_word(state, 340, (8 << 6) | (6 << 0)); in dib8000_set_13seg_channel()
2183 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); in dib8000_set_13seg_channel()
2185 dib8000_write_word(state, 228, 0); /* default value */ in dib8000_set_13seg_channel()
2186 dib8000_write_word(state, 265, 31); /* default value */ in dib8000_set_13seg_channel()
2187 dib8000_write_word(state, 205, 0x200f); /* init value */ in dib8000_set_13seg_channel()
2196 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_s… in dib8000_set_13seg_channel()
2206 dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */ in dib8000_set_subchannel_prbs()
2215 dib8000_write_word(state, 352, state->seg_diff_mask); in dib8000_small_fine_tune()
2216 dib8000_write_word(state, 353, state->seg_mask); in dib8000_small_fine_tune()
2219 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5); in dib8000_small_fine_tune()
2289 dib8000_write_word(state, 343 + i, ncoeff[i]); in dib8000_small_fine_tune()
2302 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */ in dib8000_set_sb_channel()
2303 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shi… in dib8000_set_sb_channel()
2305 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */ in dib8000_set_sb_channel()
2306 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = … in dib8000_set_sb_channel()
2314 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_sb_channel()
2318 …dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partia… in dib8000_set_sb_channel()
2320 …dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_fr… in dib8000_set_sb_channel()
2321 …dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres… in dib8000_set_sb_channel()
2327 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14)); in dib8000_set_sb_channel()
2329 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14)); in dib8000_set_sb_channel()
2332 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4); in dib8000_set_sb_channel()
2335 dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); in dib8000_set_sb_channel()
2337 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4); in dib8000_set_sb_channel()
2341 dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */ in dib8000_set_sb_channel()
2342 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */ in dib8000_set_sb_channel()
2345 dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */ in dib8000_set_sb_channel()
2349 dib8000_write_word(state, 181+i, coff[i]); in dib8000_set_sb_channel()
2350 dib8000_write_word(state, 184+i, coff[i]); in dib8000_set_sb_channel()
2358 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh … in dib8000_set_sb_channel()
2361 dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */ in dib8000_set_sb_channel()
2363 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ in dib8000_set_sb_channel()
2378 dib8000_write_word(state, 10, (seq << 4)); in dib8000_set_isdbt_common_channel()
2385 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3)); in dib8000_set_isdbt_common_channel()
2387 …dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_recep… in dib8000_set_isdbt_common_channel()
2404 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_isdbt_common_channel()
2406 dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */ in dib8000_set_isdbt_common_channel()
2416 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask); in dib8000_set_isdbt_common_channel()
2454 dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */ in dib8000_set_isdbt_common_channel()
2455 dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */ in dib8000_set_isdbt_common_channel()
2458 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */ in dib8000_set_isdbt_common_channel()
2459 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */ in dib8000_set_isdbt_common_channel()
2460 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */ in dib8000_set_isdbt_common_channel()
2463 …dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_… in dib8000_set_isdbt_common_channel()
2465 …dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be a… in dib8000_set_isdbt_common_channel()
2467 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */ in dib8000_set_isdbt_common_channel()
2468 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */ in dib8000_set_isdbt_common_channel()
2470 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ in dib8000_set_isdbt_common_channel()
2479 dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */ in dib8000_set_isdbt_common_channel()
2480 dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */ in dib8000_set_isdbt_common_channel()
2481 dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */ in dib8000_set_isdbt_common_channel()
2486 dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */ in dib8000_set_isdbt_common_channel()
2507 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff)); in dib8000_wait_lock()
2508 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff)); in dib8000_wait_lock()
2525 dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */ in dib8000_autosearch_start()
2526 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */ in dib8000_autosearch_start()
2528 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P… in dib8000_autosearch_start()
2529 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */ in dib8000_autosearch_start()
2530 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */ in dib8000_autosearch_start()
2531 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */ in dib8000_autosearch_start()
2532 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */ in dib8000_autosearch_start()
2533 …dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P… in dib8000_autosearch_start()
2540 dib8000_write_word(state, 17, 0); in dib8000_autosearch_start()
2541 dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */ in dib8000_autosearch_start()
2542 dib8000_write_word(state, 19, 0); in dib8000_autosearch_start()
2543 dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */ in dib8000_autosearch_start()
2544 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */ in dib8000_autosearch_start()
2545 dib8000_write_word(state, 22, value & 0xffff); in dib8000_autosearch_start()
2548 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha… in dib8000_autosearch_start()
2550 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha… in dib8000_autosearch_start()
2551 dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */ in dib8000_autosearch_start()
2554 dib8000_write_word(state, 356, 0); in dib8000_autosearch_start()
2555 dib8000_write_word(state, 357, 0x111); in dib8000_autosearch_start()
2557 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart… in dib8000_autosearch_start()
2558 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart… in dib8000_autosearch_start()
2559 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_… in dib8000_autosearch_start()
2576 dib8000_write_word(state, 6, 0x4); in dib8000_autosearch_start()
2578 …dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock… in dib8000_autosearch_start()
2580 dib8000_write_word(state, 7, 0x8); in dib8000_autosearch_start()
2581 dib8000_write_word(state, 8, 0x1000); in dib8000_autosearch_start()
2589 dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */ in dib8000_autosearch_start()
2592 dib8000_write_word(state, 356, 0); in dib8000_autosearch_start()
2593 dib8000_write_word(state, 357, 0xf); in dib8000_autosearch_start()
2596 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); in dib8000_autosearch_start()
2598 dib8000_write_word(state, 0, (u16)value); in dib8000_autosearch_start()
2611 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); in dib8000_autosearch_start()
2618 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 t… in dib8000_autosearch_start()
2627 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */ in dib8000_autosearch_start()
2637 dib8000_write_word(state, 6, 0x4); in dib8000_autosearch_start()
2639 dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10)); in dib8000_autosearch_start()
2641 dib8000_write_word(state, 7, 0x8); in dib8000_autosearch_start()
2642 dib8000_write_word(state, 8, 0x1000); in dib8000_autosearch_start()
2651 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); in dib8000_autosearch_start()
2653 dib8000_write_word(state, 0, (u16)value); in dib8000_autosearch_start()
2690 dib8000_write_word(state, 771, tmp & 0xfffd); in dib8000_viterbi_state()
2692 dib8000_write_word(state, 771, tmp | (1<<1)); in dib8000_viterbi_state()
2734 dib8000_write_word(state, 26, invert); in dib8000_set_dds()
2735 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff); in dib8000_set_dds()
2736 dib8000_write_word(state, 28, (u16)(dds & 0xffff)); in dib8000_set_dds()
2758 dib8000_write_word(state, 26, c->inversion ^ i); in dib8000_set_frequency_offset()
2762 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); in dib8000_set_frequency_offset()
2834 dib8000_write_word(state, 32, reg_32); in dib8000_set_isdbt_loop_params()
2835 dib8000_write_word(state, 37, reg_37); in dib8000_set_isdbt_loop_params()
2840 dib8000_write_word(state, 770, 0x4000); in dib8000_demod_restart()
2841 dib8000_write_word(state, 770, 0x0000); in dib8000_demod_restart()
2869 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4)); in dib8000_set_sync_wait()
2924 dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */ in dib8090p_init_sdram()
2926 dib8000_write_word(state, 1803, (7 << 2)); in dib8090p_init_sdram()
2929 dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */ in dib8090p_init_sdram()
2930 dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */ in dib8090p_init_sdram()
3060 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); in dib8000_tune()
3074 dib8000_write_word(state, 108, agc1); in dib8000_tune()
3075 dib8000_write_word(state, 109, agc1); in dib8000_tune()
3076 dib8000_write_word(state, 110, agc2); in dib8000_tune()
3077 dib8000_write_word(state, 111, agc2); in dib8000_tune()
3350 dib8000_write_word(state, 108, state->agc1_max); in dib8000_tune()
3351 dib8000_write_word(state, 109, state->agc1_min); in dib8000_tune()
3352 dib8000_write_word(state, 110, state->agc2_max); in dib8000_tune()
3353 dib8000_write_word(state, 111, state->agc2_min); in dib8000_tune()
4403 return dib8000_write_word(st, 299, val); in dib8000_pid_filter_ctrl()
4410 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0); in dib8000_pid_filter()
4497 …dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len … in dib8000_init()