Lines Matching full:slv
372 /* Set SLV-T Bank : 0xAE */ in cxd2841er_dvbs2_set_symbol_rate()
404 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
409 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
413 /* Set SLV-T Bank : 0xAE */ in cxd2841er_sleep_s_to_active_s()
417 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
427 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
431 /* Set SLV-T Bank : 0xA3 */ in cxd2841er_sleep_s_to_active_s()
438 /* Set SLV-T Bank : 0xAB */ in cxd2841er_sleep_s_to_active_s()
453 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
493 /* Set SLV-T Bank : 0x00 */ in cxd2841er_retune_active()
532 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_s_to_sleep_s()
540 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_s_to_sleep_s()
544 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_s_to_sleep_s()
556 /* Set SLV-T Bank : 0xAE */ in cxd2841er_active_s_to_sleep_s()
560 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_s_to_sleep_s()
576 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_s_to_shutdown()
582 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_s_to_shutdown()
600 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_shutdown()
618 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_t_to_sleep_tc()
626 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_t_to_sleep_tc()
630 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_t_to_sleep_tc()
654 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_t2_to_sleep_tc()
672 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_t2_to_sleep_tc()
676 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_t2_to_sleep_tc()
700 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_c_to_sleep_tc()
711 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_c_to_sleep_tc()
715 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_c_to_sleep_tc()
739 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_i_to_sleep_tc()
750 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_i_to_sleep_tc()
754 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_i_to_sleep_tc()
778 /* Set SLV-X Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_s()
783 /* Set SLV-X Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_s()
811 /* Set SLV-T Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_s()
838 /* Set SLV-X Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_tc()
843 /* Set SLV-X Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_tc()
868 /* Set SLV-T Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_tc()
884 /* Set SLV-T Bank : 0x00 */ in cxd2841er_tune_done()
900 /* Set SLV-T Bank : 0x00 */ in cxd2841er_set_ts_clock_mode()
910 * <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE in cxd2841er_set_ts_clock_mode()
916 * <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE in cxd2841er_set_ts_clock_mode()
922 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD in cxd2841er_set_ts_clock_mode()
928 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN in cxd2841er_set_ts_clock_mode()
933 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF in cxd2841er_set_ts_clock_mode()
940 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN in cxd2841er_set_ts_clock_mode()
981 /* Set SLV-T Bank : 0xA0 */ in cxd2841er_read_status_s()
985 * <SLV-T> A0h 11h [2] ITSLOCK in cxd2841er_read_status_s()
1008 /* Set SLV-T Bank : 0x10 */ in cxd2841er_read_status_t_t2()
1011 /* Set SLV-T Bank : 0x20 */ in cxd2841er_read_status_t_t2()
1055 /* Set SLV-T Bank : 0x60 */ in cxd2841er_read_status_i()
1138 * <SLV-T> A0h 10h [0] ITRL_LOCK in cxd2841er_get_carrier_offset_s_s2()
1145 * <SLV-T> A0h 50h [4] IHSMODE in cxd2841er_get_carrier_offset_s_s2()
1157 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16] in cxd2841er_get_carrier_offset_s_s2()
1158 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8] in cxd2841er_get_carrier_offset_s_s2()
1159 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0] in cxd2841er_get_carrier_offset_s_s2()
1482 /* Set SLV-T Bank : 0xA0 */ in cxd2841er_mon_read_ber_s()
1486 * <SLV-T> A0h 35h [0] IFVBER_VALID in cxd2841er_mon_read_ber_s()
1487 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16] in cxd2841er_mon_read_ber_s()
1488 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8] in cxd2841er_mon_read_ber_s()
1489 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0] in cxd2841er_mon_read_ber_s()
1490 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16] in cxd2841er_mon_read_ber_s()
1491 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8] in cxd2841er_mon_read_ber_s()
1492 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0] in cxd2841er_mon_read_ber_s()
1521 /* Set SLV-T Bank : 0xB2 */ in cxd2841er_mon_read_ber_s2()
1525 * <SLV-T> B2h 30h [0] IFLBER_VALID in cxd2841er_mon_read_ber_s2()
1526 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24] in cxd2841er_mon_read_ber_s2()
1527 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16] in cxd2841er_mon_read_ber_s2()
1528 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8] in cxd2841er_mon_read_ber_s2()
1529 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0] in cxd2841er_mon_read_ber_s2()
1539 /* Set SLV-T Bank : 0xA0 */ in cxd2841er_mon_read_ber_s2()
1674 /* Set SLV-T Bank : 0xA1 */ in cxd2841er_dvbs_read_snr()
1678 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY in cxd2841er_dvbs_read_snr()
1679 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8] in cxd2841er_dvbs_read_snr()
1680 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0] in cxd2841er_dvbs_read_snr()
1924 /* Set SLV-T Bank : 0xA0 */ in cxd2841er_read_agc_gain_s()
1928 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8] in cxd2841er_read_agc_gain_s()
1929 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0] in cxd2841er_read_agc_gain_s()
2133 /* Set SLV-T Bank : 0x2E */ in cxd2841er_dvbt2_set_profile()
2137 /* Set SLV-T Bank : 0x2B */ in cxd2841er_dvbt2_set_profile()
2155 /* Set SLV-T Bank : 0x23 */ in cxd2841er_dvbt2_set_plp_config()
2252 /* Set SLV-T Bank : 0x20 */ in cxd2841er_sleep_tc_to_active_t2_band()
2261 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2266 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2291 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2296 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2321 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2326 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2351 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2356 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2381 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2386 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2475 /* Set SLV-T Bank : 0x13 */ in cxd2841er_sleep_tc_to_active_t_band()
2482 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t_band()
2688 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_i_band()
2858 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_c_band()
2871 /* Set SLV-T Bank : 0x40 */ in cxd2841er_sleep_tc_to_active_c_band()
2901 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t()
2905 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t()
2923 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t()
2927 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_t()
2931 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t()
2936 /* Set SLV-T Bank : 0x18 */ in cxd2841er_sleep_tc_to_active_t()
2943 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t()
2950 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t()
2958 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t()
2975 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t2()
2979 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t2()
3002 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2()
3006 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_t2()
3010 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2()
3015 /* Set SLV-T Bank : 0x20 */ in cxd2841er_sleep_tc_to_active_t2()
3019 /* Set SLV-T Bank : 0x2b */ in cxd2841er_sleep_tc_to_active_t2()
3022 /* Set SLV-T Bank : 0x23 */ in cxd2841er_sleep_tc_to_active_t2()
3026 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t2()
3037 /* Set SLV-T Bank : 0x2a */ in cxd2841er_sleep_tc_to_active_t2()
3040 /* Set SLV-T Bank : 0x2b */ in cxd2841er_sleep_tc_to_active_t2()
3046 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_t2()
3053 /* Set SLV-T Bank : 0x20 */ in cxd2841er_sleep_tc_to_active_t2()
3066 /* Set SLV-T Bank : 0x24 */ in cxd2841er_sleep_tc_to_active_t2()
3084 /* Set SLV-T Bank : 0x25 */ in cxd2841er_sleep_tc_to_active_t2()
3088 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2()
3092 /* Set SLV-T Bank : 0x2B */ in cxd2841er_sleep_tc_to_active_t2()
3097 /* Set SLV-T Bank : 0x2D */ in cxd2841er_sleep_tc_to_active_t2()
3103 /* Set SLV-T Bank : 0x5E */ in cxd2841er_sleep_tc_to_active_t2()
3112 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t2()
3132 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_i()
3136 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_i()
3158 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_i()
3162 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_i()
3172 /* Set SLV-T Bank : 0x15 */ in cxd2841er_sleep_tc_to_active_i()
3175 /* Set SLV-T Bank : 0x1E */ in cxd2841er_sleep_tc_to_active_i()
3178 /* Set SLV-T Bank : 0x63 */ in cxd2841er_sleep_tc_to_active_i()
3183 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_i()
3186 /* Set SLV-T Bank : 0x60 */ in cxd2841er_sleep_tc_to_active_i()
3191 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_i()
3208 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_c()
3212 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_c()
3227 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_c()
3231 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_c()
3235 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_c()
3240 /* Set SLV-T Bank : 0x40 */ in cxd2841er_sleep_tc_to_active_c()
3244 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_c()
3251 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_c()