Lines Matching +full:imx6sx +full:- +full:mu
1 // SPDX-License-Identifier: GPL-2.0
24 /* TX0/RX0/RXDB[0-3] */
118 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
119 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
120 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
123 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
125 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
127 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
129 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
130 /* MU reset */
142 iowrite32(val, priv->base + offs); in imx_mu_write()
147 return ioread32(priv->base + offs); in imx_mu_read()
156 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); in imx_mu_tx_waiting_write()
159 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_tx_waiting_write()
160 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); in imx_mu_tx_waiting_write()
164 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", in imx_mu_tx_waiting_write()
166 return -ETIME; in imx_mu_tx_waiting_write()
169 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); in imx_mu_tx_waiting_write()
180 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); in imx_mu_rx_waiting_read()
183 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_rx_waiting_read()
184 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); in imx_mu_rx_waiting_read()
188 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", in imx_mu_rx_waiting_read()
190 return -ETIME; in imx_mu_rx_waiting_read()
193 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); in imx_mu_rx_waiting_read()
194 dev_dbg(priv->dev, "Read %.8x\n", *val); in imx_mu_rx_waiting_read()
204 spin_lock_irqsave(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
205 val = imx_mu_read(priv, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
208 imx_mu_write(priv, val, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
209 spin_unlock_irqrestore(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
220 switch (cp->type) { in imx_mu_generic_tx()
222 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); in imx_mu_generic_tx()
223 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_generic_tx()
226 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); in imx_mu_generic_tx()
227 tasklet_schedule(&cp->txdb_tasklet); in imx_mu_generic_tx()
230 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_generic_tx()
231 return -EINVAL; in imx_mu_generic_tx()
242 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4); in imx_mu_generic_rx()
243 mbox_chan_received_data(cp->chan, (void *)&dat); in imx_mu_generic_rx()
251 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), in imx_mu_generic_rxdb()
252 priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_generic_rxdb()
253 mbox_chan_received_data(cp->chan, NULL); in imx_mu_generic_rxdb()
265 if (priv->dcfg->type & IMX_MU_V2_S4) { in imx_mu_specific_tx()
266 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; in imx_mu_specific_tx()
270 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; in imx_mu_specific_tx()
275 switch (cp->type) { in imx_mu_specific_tx()
278 * msg->hdr.size specifies the number of u32 words while in imx_mu_specific_tx()
287 …dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, si… in imx_mu_specific_tx()
288 return -EINVAL; in imx_mu_specific_tx()
292 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); in imx_mu_specific_tx()
294 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], in imx_mu_specific_tx()
296 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), in imx_mu_specific_tx()
299 dev_err(priv->dev, "Send data index: %d timeout\n", i); in imx_mu_specific_tx()
302 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); in imx_mu_specific_tx()
305 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_specific_tx()
308 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_specific_tx()
309 return -EINVAL; in imx_mu_specific_tx()
322 data = (u32 *)priv->msg; in imx_mu_specific_rx()
324 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0)); in imx_mu_specific_rx()
325 *data++ = imx_mu_read(priv, priv->dcfg->xRR); in imx_mu_specific_rx()
327 if (priv->dcfg->type & IMX_MU_V2_S4) { in imx_mu_specific_rx()
328 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size; in imx_mu_specific_rx()
331 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size; in imx_mu_specific_rx()
336 …dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, si… in imx_mu_specific_rx()
337 return -EINVAL; in imx_mu_specific_rx()
341 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, in imx_mu_specific_rx()
342 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, in imx_mu_specific_rx()
345 dev_err(priv->dev, "timeout read idx %d\n", i); in imx_mu_specific_rx()
348 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); in imx_mu_specific_rx()
351 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); in imx_mu_specific_rx()
352 mbox_chan_received_data(cp->chan, (void *)priv->msg); in imx_mu_specific_rx()
366 dev_dbg(priv->dev, "Sending message\n"); in imx_mu_seco_tx()
368 switch (cp->type) { in imx_mu_seco_tx()
370 byte_size = msg->hdr.size * sizeof(u32); in imx_mu_seco_tx()
376 dev_err(priv->dev, in imx_mu_seco_tx()
379 return -EINVAL; in imx_mu_seco_tx()
386 dev_dbg(priv->dev, "Sending header\n"); in imx_mu_seco_tx()
387 imx_mu_write(priv, *arg++, priv->dcfg->xTR); in imx_mu_seco_tx()
390 dev_dbg(priv->dev, "Sending signaling\n"); in imx_mu_seco_tx()
392 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); in imx_mu_seco_tx()
395 for (i = 1; i < 4 && i < msg->hdr.size; i++) { in imx_mu_seco_tx()
396 dev_dbg(priv->dev, "Sending word %d\n", i); in imx_mu_seco_tx()
398 priv->dcfg->xTR + (i % 4) * 4); in imx_mu_seco_tx()
402 for (; i < msg->hdr.size; i++) { in imx_mu_seco_tx()
403 dev_dbg(priv->dev, "Sending word %d\n", i); in imx_mu_seco_tx()
406 dev_err(priv->dev, "Timeout tx %d\n", i); in imx_mu_seco_tx()
412 tasklet_schedule(&cp->txdb_tasklet); in imx_mu_seco_tx()
416 dev_warn_ratelimited(priv->dev, in imx_mu_seco_tx()
418 cp->type); in imx_mu_seco_tx()
419 return -EINVAL; in imx_mu_seco_tx()
433 dev_dbg(priv->dev, "Receiving message\n"); in imx_mu_seco_rxdb()
436 dev_dbg(priv->dev, "Receiving header\n"); in imx_mu_seco_rxdb()
437 *data++ = imx_mu_read(priv, priv->dcfg->xRR); in imx_mu_seco_rxdb()
440 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", in imx_mu_seco_rxdb()
442 err = -EINVAL; in imx_mu_seco_rxdb()
448 dev_dbg(priv->dev, "Receiving word %d\n", i); in imx_mu_seco_rxdb()
451 dev_err(priv->dev, "Timeout rx %d\n", i); in imx_mu_seco_rxdb()
457 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), in imx_mu_seco_rxdb()
458 priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_seco_rxdb()
464 dev_dbg(priv->dev, "Sending message to client\n"); in imx_mu_seco_rxdb()
465 mbox_chan_received_data(cp->chan, (void *)&msg); in imx_mu_seco_rxdb()
470 mbox_chan_received_data(cp->chan, ERR_PTR(err)); in imx_mu_seco_rxdb()
480 mbox_chan_txdone(cp->chan, 0); in imx_mu_txdb_tasklet()
486 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_isr()
487 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_isr()
490 switch (cp->type) { in imx_mu_isr()
492 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]); in imx_mu_isr()
493 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_isr()
494 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
495 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
498 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]); in imx_mu_isr()
499 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_isr()
500 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
501 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
504 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]); in imx_mu_isr()
505 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_isr()
506 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
507 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
512 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", in imx_mu_isr()
513 cp->type); in imx_mu_isr()
520 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
521 (cp->type == IMX_MU_TYPE_TX)) { in imx_mu_isr()
522 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
524 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
525 (cp->type == IMX_MU_TYPE_RX)) { in imx_mu_isr()
526 priv->dcfg->rx(priv, cp); in imx_mu_isr()
527 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
528 (cp->type == IMX_MU_TYPE_RXDB)) { in imx_mu_isr()
529 priv->dcfg->rxdb(priv, cp); in imx_mu_isr()
531 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); in imx_mu_isr()
535 if (priv->suspend) in imx_mu_isr()
543 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_send_data()
544 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_send_data()
546 return priv->dcfg->tx(priv, cp, data); in imx_mu_send_data()
551 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_startup()
552 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_startup()
556 pm_runtime_get_sync(priv->dev); in imx_mu_startup()
557 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_startup()
559 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, in imx_mu_startup()
564 /* IPC MU should be with IRQF_NO_SUSPEND set */ in imx_mu_startup()
565 if (!priv->dev->pm_domain) in imx_mu_startup()
568 if (!(priv->dcfg->type & IMX_MU_V2_IRQ)) in imx_mu_startup()
571 ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan); in imx_mu_startup()
573 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]); in imx_mu_startup()
577 switch (cp->type) { in imx_mu_startup()
579 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_startup()
582 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_startup()
593 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_shutdown()
594 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_shutdown()
598 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_shutdown()
599 tasklet_kill(&cp->txdb_tasklet); in imx_mu_shutdown()
600 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
604 switch (cp->type) { in imx_mu_shutdown()
606 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
609 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
612 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
615 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); in imx_mu_shutdown()
616 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, in imx_mu_shutdown()
617 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); in imx_mu_shutdown()
619 dev_warn(priv->dev, "RST channel timeout\n"); in imx_mu_shutdown()
625 free_irq(priv->irq[cp->type], chan); in imx_mu_shutdown()
626 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
640 if (sp->args_count != 2) { in imx_mu_specific_xlate()
641 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_specific_xlate()
642 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
645 type = sp->args[0]; /* channel type */ in imx_mu_specific_xlate()
646 idx = sp->args[1]; /* index */ in imx_mu_specific_xlate()
652 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); in imx_mu_specific_xlate()
659 dev_err(mbox->dev, "Invalid chan type: %d\n", type); in imx_mu_specific_xlate()
660 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
663 if (chan >= mbox->num_chans) { in imx_mu_specific_xlate()
664 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_specific_xlate()
665 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
668 return &mbox->chans[chan]; in imx_mu_specific_xlate()
676 if (sp->args_count != 2) { in imx_mu_xlate()
677 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_xlate()
678 return ERR_PTR(-EINVAL); in imx_mu_xlate()
681 type = sp->args[0]; /* channel type */ in imx_mu_xlate()
682 idx = sp->args[1]; /* index */ in imx_mu_xlate()
685 if (chan >= mbox->num_chans) { in imx_mu_xlate()
686 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_xlate()
687 return ERR_PTR(-EINVAL); in imx_mu_xlate()
690 return &mbox->chans[chan]; in imx_mu_xlate()
698 if (sp->args_count < 1) { in imx_mu_seco_xlate()
699 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_seco_xlate()
700 return ERR_PTR(-EINVAL); in imx_mu_seco_xlate()
703 type = sp->args[0]; /* channel type */ in imx_mu_seco_xlate()
707 dev_err(mbox->dev, "Invalid type: %d\n", type); in imx_mu_seco_xlate()
708 return ERR_PTR(-EINVAL); in imx_mu_seco_xlate()
720 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_generic()
722 cp->idx = i % 4; in imx_mu_init_generic()
723 cp->type = i >> 2; in imx_mu_init_generic()
724 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_generic()
725 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_generic()
726 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_generic()
727 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_init_generic()
730 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_init_generic()
731 priv->mbox.of_xlate = imx_mu_xlate; in imx_mu_init_generic()
733 if (priv->side_b) in imx_mu_init_generic()
736 /* Set default MU configuration */ in imx_mu_init_generic()
738 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); in imx_mu_init_generic()
741 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_init_generic()
742 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_init_generic()
746 imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); in imx_mu_init_generic()
752 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; in imx_mu_init_specific()
755 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_specific()
757 cp->idx = i < 2 ? 0 : i - 2; in imx_mu_init_specific()
758 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; in imx_mu_init_specific()
759 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_specific()
760 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_specific()
761 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_specific()
762 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_init_specific()
765 priv->mbox.num_chans = num_chans; in imx_mu_init_specific()
766 priv->mbox.of_xlate = imx_mu_specific_xlate; in imx_mu_init_specific()
768 /* Set default MU configuration */ in imx_mu_init_specific()
770 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); in imx_mu_init_specific()
776 priv->mbox.of_xlate = imx_mu_seco_xlate; in imx_mu_init_seco()
781 struct device *dev = &pdev->dev; in imx_mu_probe()
782 struct device_node *np = dev->of_node; in imx_mu_probe()
790 return -ENOMEM; in imx_mu_probe()
792 priv->dev = dev; in imx_mu_probe()
794 priv->base = devm_platform_ioremap_resource(pdev, 0); in imx_mu_probe()
795 if (IS_ERR(priv->base)) in imx_mu_probe()
796 return PTR_ERR(priv->base); in imx_mu_probe()
800 return -EINVAL; in imx_mu_probe()
801 priv->dcfg = dcfg; in imx_mu_probe()
802 if (priv->dcfg->type & IMX_MU_V2_IRQ) { in imx_mu_probe()
803 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx"); in imx_mu_probe()
804 if (priv->irq[IMX_MU_TYPE_TX] < 0) in imx_mu_probe()
805 return priv->irq[IMX_MU_TYPE_TX]; in imx_mu_probe()
806 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx"); in imx_mu_probe()
807 if (priv->irq[IMX_MU_TYPE_RX] < 0) in imx_mu_probe()
808 return priv->irq[IMX_MU_TYPE_RX]; in imx_mu_probe()
815 priv->irq[i] = ret; in imx_mu_probe()
818 if (priv->dcfg->type & IMX_MU_V2_S4) in imx_mu_probe()
823 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL); in imx_mu_probe()
824 if (!priv->msg) in imx_mu_probe()
825 return -ENOMEM; in imx_mu_probe()
827 priv->clk = devm_clk_get(dev, NULL); in imx_mu_probe()
828 if (IS_ERR(priv->clk)) { in imx_mu_probe()
829 if (PTR_ERR(priv->clk) != -ENOENT) in imx_mu_probe()
830 return PTR_ERR(priv->clk); in imx_mu_probe()
832 priv->clk = NULL; in imx_mu_probe()
835 ret = clk_prepare_enable(priv->clk); in imx_mu_probe()
841 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); in imx_mu_probe()
843 priv->dcfg->init(priv); in imx_mu_probe()
845 spin_lock_init(&priv->xcr_lock); in imx_mu_probe()
847 priv->mbox.dev = dev; in imx_mu_probe()
848 priv->mbox.ops = &imx_mu_ops; in imx_mu_probe()
849 priv->mbox.chans = priv->mbox_chans; in imx_mu_probe()
850 priv->mbox.txdone_irq = true; in imx_mu_probe()
854 ret = devm_mbox_controller_register(dev, &priv->mbox); in imx_mu_probe()
856 clk_disable_unprepare(priv->clk); in imx_mu_probe()
870 clk_disable_unprepare(priv->clk); in imx_mu_probe()
876 clk_disable_unprepare(priv->clk); in imx_mu_probe()
884 pm_runtime_disable(priv->dev); in imx_mu_remove()
968 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
969 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
970 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
971 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
972 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
973 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
974 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
984 if (!priv->clk) { in imx_mu_suspend_noirq()
986 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); in imx_mu_suspend_noirq()
989 priv->suspend = true; in imx_mu_suspend_noirq()
1000 * ONLY restore MU when context lost, the TIE could in imx_mu_resume_noirq()
1001 * be set during noirq resume as there is MU data in imx_mu_resume_noirq()
1003 * value will overwrite the TIE and cause MU data in imx_mu_resume_noirq()
1007 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) { in imx_mu_resume_noirq()
1009 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); in imx_mu_resume_noirq()
1012 priv->suspend = false; in imx_mu_resume_noirq()
1021 clk_disable_unprepare(priv->clk); in imx_mu_runtime_suspend()
1031 ret = clk_prepare_enable(priv->clk); in imx_mu_runtime_resume()