Lines Matching +full:tx +full:- +full:mailbox +full:- +full:count
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Broadcom PDC Mailbox Driver
9 * offload engines. For example, the PDC driver works with both SPU-M and SPU2
13 * The PDC driver registers with the Linux mailbox framework as a mailbox
15 * a mailbox channel. The PDC driver uses interrupts to determine when data
25 * descriptors from the tx and rx ring, thus processing one response at a time.
42 #include <linux/mailbox/brcm-message.h>
44 #include <linux/dma-direction.h>
45 #include <linux/dma-mapping.h>
55 * Minimum number of ring descriptor entries that must be free to tell mailbox
73 #define PREVTXD(i, max_mask) TXD((i) - 1, (max_mask))
75 #define PREVRXD(i, max_mask) RXD((i) - 1, (max_mask))
76 #define NTXDACTIVE(h, t, max_mask) TXD((t) - (h), (max_mask))
77 #define NRXDACTIVE(h, t, max_mask) RXD((t) - (h), (max_mask))
89 * Interrupt mask and status definitions. Enable interrupts for tx and rx on
115 * 11 - PtyChkDisable - parity check is disabled
116 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
120 /* Bit in tx control reg to enable tx channel */
125 * 7:1 - RcvOffset - size in bytes of status region at start of rx frame buf
126 * 9 - SepRxHdrDescEn - place start of new frames only in descriptors
128 * 10 - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all
131 * 11 - PtyChkDisable - parity check is disabled
132 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
139 #define CRYPTO_D64_RS0_CD_MASK ((PDC_RING_ENTRIES * RING_ENTRY_SIZE) - 1)
168 u32 ctrl2; /* buffer count and address extension */
177 u32 addrlow; /* descriptor ring base address low 32-bits */
192 struct dma64_regs dmaxmt; /* dma tx */
240 u32 PAD[11]; /* 0x1b4-1dc */
247 struct dma64 dmaregs[PDC_NUM_DMA_RINGS]; /* 0x0200 - 0x2fc */
289 * Each PDC instance has a mailbox controller. PDC receives request
291 * mailbox framework.
317 * The base virtual address of DMA tx/rx descriptor rings. Corresponding
325 struct dma64_regs *txregs_64; /* dma tx engine registers */
332 struct dma64dd *txd_64; /* tx descriptor ring */
336 u32 ntxd; /* # tx descriptors */
339 u32 ntxpost; /* max number of tx buffers that can be posted */
342 * Index of next tx descriptor to reclaim. That is, the descriptor
343 * index of the oldest tx buffer for which the host has yet to process
351 * the rxin_numd count for a message. Updated to rxout when the host
356 /* Index of next tx descriptor to post. */
360 * Number of tx descriptors associated with the message that starts
361 * at this tx descriptor index.
374 * the rxin_numd count for a message. Updated to rxout when the host
401 u32 last_tx_not_done; /* too few tx descriptors to indicate done */
402 u32 tx_ring_full; /* unable to accept msg because tx ring full */
404 u32 txnobuf; /* unable to create tx descriptor */
406 u32 rx_oflow; /* count of rx overflows */
408 /* hardware type - FA2 or PDC/MDE */
425 size_t count, loff_t *offp) in pdc_debugfs_read() argument
435 return -ENOMEM; in pdc_debugfs_read()
437 pdcs = filp->private_data; in pdc_debugfs_read()
439 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
440 "SPU %u stats:\n", pdcs->pdc_idx); in pdc_debugfs_read()
441 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
443 pdcs->pdc_requests); in pdc_debugfs_read()
444 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
446 pdcs->pdc_replies); in pdc_debugfs_read()
447 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
448 "Tx not done.....................%u\n", in pdc_debugfs_read()
449 pdcs->last_tx_not_done); in pdc_debugfs_read()
450 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
451 "Tx ring full....................%u\n", in pdc_debugfs_read()
452 pdcs->tx_ring_full); in pdc_debugfs_read()
453 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
455 pdcs->rx_ring_full); in pdc_debugfs_read()
456 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
457 "Tx desc write fail. Ring full...%u\n", in pdc_debugfs_read()
458 pdcs->txnobuf); in pdc_debugfs_read()
459 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
461 pdcs->rxnobuf); in pdc_debugfs_read()
462 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
464 pdcs->rx_oflow); in pdc_debugfs_read()
465 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
467 NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, in pdc_debugfs_read()
468 pdcs->nrxpost)); in pdc_debugfs_read()
473 ret = simple_read_from_buffer(ubuf, count, offp, buf, out_offset); in pdc_debugfs_read()
485 * pdc_setup_debugfs() - Create the debug FS directories. If the top-level
497 snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx); in pdc_setup_debugfs()
513 * pdc_build_rxd() - Build DMA descriptor to receive SPU result.
523 struct device *dev = &pdcs->pdev->dev; in pdc_build_rxd()
524 struct dma64dd *rxd = &pdcs->rxd_64[pdcs->rxout]; in pdc_build_rxd()
528 pdcs->pdc_idx, pdcs->rxout, buf_len, flags); in pdc_build_rxd()
530 rxd->addrlow = cpu_to_le32(lower_32_bits(dma_addr)); in pdc_build_rxd()
531 rxd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); in pdc_build_rxd()
532 rxd->ctrl1 = cpu_to_le32(flags); in pdc_build_rxd()
533 rxd->ctrl2 = cpu_to_le32(buf_len); in pdc_build_rxd()
536 pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost); in pdc_build_rxd()
540 * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to
544 * @buf_len: Length of tx buffer, in bytes
551 struct device *dev = &pdcs->pdev->dev; in pdc_build_txd()
552 struct dma64dd *txd = &pdcs->txd_64[pdcs->txout]; in pdc_build_txd()
555 "Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n", in pdc_build_txd()
556 pdcs->pdc_idx, pdcs->txout, buf_len, flags); in pdc_build_txd()
558 txd->addrlow = cpu_to_le32(lower_32_bits(dma_addr)); in pdc_build_txd()
559 txd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); in pdc_build_txd()
560 txd->ctrl1 = cpu_to_le32(flags); in pdc_build_txd()
561 txd->ctrl2 = cpu_to_le32(buf_len); in pdc_build_txd()
564 pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost); in pdc_build_txd()
568 * pdc_receive_one() - Receive a response message from a given SPU.
575 * -EAGAIN indicates that no response message is available
576 * -EIO an error occurred
581 struct device *dev = &pdcs->pdev->dev; in pdc_receive_one()
593 mbc = &pdcs->mbc; in pdc_receive_one()
594 chan = &mbc->chans[0]; in pdc_receive_one()
602 frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost); in pdc_receive_one()
604 (frags_rdy < pdcs->rx_ctx[pdcs->rxin].rxin_numd)) in pdc_receive_one()
606 return -EAGAIN; in pdc_receive_one()
608 num_frags = pdcs->txin_numd[pdcs->txin]; in pdc_receive_one()
611 dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin], in pdc_receive_one()
612 sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE); in pdc_receive_one()
614 pdcs->txin = (pdcs->txin + num_frags) & pdcs->ntxpost; in pdc_receive_one()
616 dev_dbg(dev, "PDC %u reclaimed %d tx descriptors", in pdc_receive_one()
617 pdcs->pdc_idx, num_frags); in pdc_receive_one()
619 rx_idx = pdcs->rxin; in pdc_receive_one()
620 rx_ctx = &pdcs->rx_ctx[rx_idx]; in pdc_receive_one()
621 num_frags = rx_ctx->rxin_numd; in pdc_receive_one()
623 mssg.ctx = rx_ctx->rxp_ctx; in pdc_receive_one()
624 rx_ctx->rxp_ctx = NULL; in pdc_receive_one()
625 resp_hdr = rx_ctx->resp_hdr; in pdc_receive_one()
626 resp_hdr_daddr = rx_ctx->resp_hdr_daddr; in pdc_receive_one()
627 dma_unmap_sg(dev, rx_ctx->dst_sg, sg_nents(rx_ctx->dst_sg), in pdc_receive_one()
630 pdcs->rxin = (pdcs->rxin + num_frags) & pdcs->nrxpost; in pdc_receive_one()
633 pdcs->pdc_idx, num_frags); in pdc_receive_one()
637 pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin, in pdc_receive_one()
638 pdcs->rxout, pdcs->last_rx_curr); in pdc_receive_one()
640 if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) { in pdc_receive_one()
642 * For SPU-M, get length of response msg and rx overflow status. in pdc_receive_one()
652 pdcs->rx_oflow++; in pdc_receive_one()
656 return -EIO; in pdc_receive_one()
660 dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr); in pdc_receive_one()
664 pdcs->pdc_replies++; in pdc_receive_one()
669 * pdc_receive() - Process as many responses as are available in the rx ring.
681 pdcs->last_rx_curr = in pdc_receive()
682 (ioread32((const void __iomem *)&pdcs->rxregs_64->status0) & in pdc_receive()
694 * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit
717 u32 desc_w = 0; /* Number of tx descriptors written */ in pdc_tx_list_sg_add()
723 /* check whether enough tx descriptors are available */ in pdc_tx_list_sg_add()
724 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, in pdc_tx_list_sg_add()
725 pdcs->ntxpost); in pdc_tx_list_sg_add()
727 pdcs->txnobuf++; in pdc_tx_list_sg_add()
728 return -ENOSPC; in pdc_tx_list_sg_add()
731 /* build tx descriptors */ in pdc_tx_list_sg_add()
732 if (pdcs->tx_msg_start == pdcs->txout) { in pdc_tx_list_sg_add()
734 pdcs->txin_numd[pdcs->tx_msg_start] = 0; in pdc_tx_list_sg_add()
735 pdcs->src_sg[pdcs->txout] = sg; in pdc_tx_list_sg_add()
740 if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) in pdc_tx_list_sg_add()
755 bufcnt -= PDC_DMA_BUF_MAX; in pdc_tx_list_sg_add()
757 if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) in pdc_tx_list_sg_add()
771 pdcs->txin_numd[pdcs->tx_msg_start] += desc_w; in pdc_tx_list_sg_add()
777 * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx
781 * Sets the index of the last descriptor written in both the rx and tx ring.
792 iowrite32(pdcs->rxout << 4, &pdcs->rxregs_64->ptr); in pdc_tx_list_final()
793 iowrite32(pdcs->txout << 4, &pdcs->txregs_64->ptr); in pdc_tx_list_final()
794 pdcs->pdc_requests++; in pdc_tx_list_final()
800 * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC.
803 * mailbox client
807 * response. For example, with SPU-M, the metadata is a 32-byte DMA header and
808 * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and
824 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rx_list_init()
825 pdcs->nrxpost); in pdc_rx_list_init()
827 pdcs->rxnobuf++; in pdc_rx_list_init()
828 return -ENOSPC; in pdc_rx_list_init()
832 vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr); in pdc_rx_list_init()
834 return -ENOMEM; in pdc_rx_list_init()
837 * Update msg_start indexes for both tx and rx to indicate the start in pdc_rx_list_init()
841 pdcs->rx_msg_start = pdcs->rxout; in pdc_rx_list_init()
842 pdcs->tx_msg_start = pdcs->txout; in pdc_rx_list_init()
846 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd = 1; in pdc_rx_list_init()
848 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_init()
851 rx_ctx = &pdcs->rx_ctx[pdcs->rxout]; in pdc_rx_list_init()
852 rx_ctx->rxp_ctx = ctx; in pdc_rx_list_init()
853 rx_ctx->dst_sg = dst_sg; in pdc_rx_list_init()
854 rx_ctx->resp_hdr = vaddr; in pdc_rx_list_init()
855 rx_ctx->resp_hdr_daddr = daddr; in pdc_rx_list_init()
856 pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags); in pdc_rx_list_init()
861 * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive
884 u32 desc_w = 0; /* Number of tx descriptors written */ in pdc_rx_list_sg_add()
890 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rx_list_sg_add()
891 pdcs->nrxpost); in pdc_rx_list_sg_add()
893 pdcs->rxnobuf++; in pdc_rx_list_sg_add()
894 return -ENOSPC; in pdc_rx_list_sg_add()
898 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_sg_add()
912 bufcnt -= PDC_DMA_BUF_MAX; in pdc_rx_list_sg_add()
914 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_sg_add()
923 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd += desc_w; in pdc_rx_list_sg_add()
929 * pdc_irq_handler() - Interrupt handler called in interrupt context.
944 u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); in pdc_irq_handler()
950 iowrite32(0, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_irq_handler()
953 iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); in pdc_irq_handler()
956 tasklet_schedule(&pdcs->rx_tasklet); in pdc_irq_handler()
961 * pdc_tasklet_cb() - Tasklet callback that runs the deferred processing after
972 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_tasklet_cb()
976 * pdc_ring_init() - Allocate DMA rings and initialize constant fields of
989 struct device *dev = &pdcs->pdev->dev; in pdc_ring_init()
990 struct pdc_ring_alloc tx; in pdc_ring_init() local
993 /* Allocate tx ring */ in pdc_ring_init()
994 tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase); in pdc_ring_init()
995 if (unlikely(!tx.vbase)) { in pdc_ring_init()
996 err = -ENOMEM; in pdc_ring_init()
1001 rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase); in pdc_ring_init()
1003 err = -ENOMEM; in pdc_ring_init()
1007 dev_dbg(dev, " - base DMA addr of tx ring %pad", &tx.dmabase); in pdc_ring_init()
1008 dev_dbg(dev, " - base virtual addr of tx ring %p", tx.vbase); in pdc_ring_init()
1009 dev_dbg(dev, " - base DMA addr of rx ring %pad", &rx.dmabase); in pdc_ring_init()
1010 dev_dbg(dev, " - base virtual addr of rx ring %p", rx.vbase); in pdc_ring_init()
1012 memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx)); in pdc_ring_init()
1013 memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx)); in pdc_ring_init()
1015 pdcs->rxin = 0; in pdc_ring_init()
1016 pdcs->rx_msg_start = 0; in pdc_ring_init()
1017 pdcs->last_rx_curr = 0; in pdc_ring_init()
1018 pdcs->rxout = 0; in pdc_ring_init()
1019 pdcs->txin = 0; in pdc_ring_init()
1020 pdcs->tx_msg_start = 0; in pdc_ring_init()
1021 pdcs->txout = 0; in pdc_ring_init()
1024 pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase; in pdc_ring_init()
1025 pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase; in pdc_ring_init()
1028 dma_reg = &pdcs->regs->dmaregs[ringset]; in pdc_ring_init()
1030 /* But first disable DMA and set curptr to 0 for both TX & RX */ in pdc_ring_init()
1031 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_ring_init()
1032 iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)), in pdc_ring_init()
1033 &dma_reg->dmarcv.control); in pdc_ring_init()
1034 iowrite32(0, &dma_reg->dmaxmt.ptr); in pdc_ring_init()
1035 iowrite32(0, &dma_reg->dmarcv.ptr); in pdc_ring_init()
1038 iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase), in pdc_ring_init()
1039 &dma_reg->dmaxmt.addrlow); in pdc_ring_init()
1040 iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase), in pdc_ring_init()
1041 &dma_reg->dmaxmt.addrhigh); in pdc_ring_init()
1043 iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase), in pdc_ring_init()
1044 &dma_reg->dmarcv.addrlow); in pdc_ring_init()
1045 iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase), in pdc_ring_init()
1046 &dma_reg->dmarcv.addrhigh); in pdc_ring_init()
1048 /* Re-enable DMA */ in pdc_ring_init()
1049 iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control); in pdc_ring_init()
1050 iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)), in pdc_ring_init()
1051 &dma_reg->dmarcv.control); in pdc_ring_init()
1055 /* Every tx descriptor can be used for start of frame. */ in pdc_ring_init()
1056 if (i != pdcs->ntxpost) { in pdc_ring_init()
1058 &pdcs->txd_64[i].ctrl1); in pdc_ring_init()
1062 D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1); in pdc_ring_init()
1066 if (i != pdcs->nrxpost) { in pdc_ring_init()
1068 &pdcs->rxd_64[i].ctrl1); in pdc_ring_init()
1072 &pdcs->rxd_64[i].ctrl1); in pdc_ring_init()
1078 dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase); in pdc_ring_init()
1085 if (pdcs->tx_ring_alloc.vbase) { in pdc_ring_free()
1086 dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase, in pdc_ring_free()
1087 pdcs->tx_ring_alloc.dmabase); in pdc_ring_free()
1088 pdcs->tx_ring_alloc.vbase = NULL; in pdc_ring_free()
1091 if (pdcs->rx_ring_alloc.vbase) { in pdc_ring_free()
1092 dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase, in pdc_ring_free()
1093 pdcs->rx_ring_alloc.dmabase); in pdc_ring_free()
1094 pdcs->rx_ring_alloc.vbase = NULL; in pdc_ring_free()
1099 * pdc_desc_count() - Count the number of DMA descriptors that will be required
1109 cnt += ((sg->length / PDC_DMA_BUF_MAX) + 1); in pdc_desc_count()
1116 * pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors
1119 * @tx_cnt: The number of descriptors required in the tx ring
1131 /* Check if the tx and rx rings are likely to have enough space */ in pdc_rings_full()
1132 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rings_full()
1133 pdcs->nrxpost); in pdc_rings_full()
1135 pdcs->rx_ring_full++; in pdc_rings_full()
1140 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, in pdc_rings_full()
1141 pdcs->ntxpost); in pdc_rings_full()
1143 pdcs->tx_ring_full++; in pdc_rings_full()
1151 * pdc_last_tx_done() - If both the tx and rx rings have at least
1152 * PDC_RING_SPACE_MIN descriptors available, then indicate that the mailbox
1154 * @chan: mailbox channel to check
1159 struct pdc_state *pdcs = chan->con_priv; in pdc_last_tx_done()
1164 pdcs->last_tx_not_done++; in pdc_last_tx_done()
1173 * pdc_send_data() - mailbox send_data function
1174 * @chan: The mailbox channel on which the data is sent. The channel
1176 * @data: The mailbox message to be sent. The message must be a
1179 * This function is registered as the send_data function for the mailbox
1180 * controller. From the destination scatterlist in the mailbox message, it
1182 * scatterlist, it creates a sequence of transmit descriptors in the tx ring.
1183 * After creating the descriptors, it writes the rx ptr and tx ptr registers to
1187 * the mailbox message.
1190 * -ENOTSUPP if the mailbox message is a type this driver does not
1196 struct pdc_state *pdcs = chan->con_priv; in pdc_send_data()
1197 struct device *dev = &pdcs->pdev->dev; in pdc_send_data()
1206 if (unlikely(mssg->type != BRCM_MESSAGE_SPU)) in pdc_send_data()
1207 return -ENOTSUPP; in pdc_send_data()
1209 src_nent = sg_nents(mssg->spu.src); in pdc_send_data()
1211 nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE); in pdc_send_data()
1213 return -EIO; in pdc_send_data()
1216 dst_nent = sg_nents(mssg->spu.dst); in pdc_send_data()
1218 nent = dma_map_sg(dev, mssg->spu.dst, dst_nent, in pdc_send_data()
1221 dma_unmap_sg(dev, mssg->spu.src, src_nent, in pdc_send_data()
1223 return -EIO; in pdc_send_data()
1228 * Check if the tx and rx rings have enough space. Do this prior to in pdc_send_data()
1229 * writing any tx or rx descriptors. Need to ensure that we do not write in pdc_send_data()
1231 * corresponding tx descriptors don't fit. Note that we want this check in pdc_send_data()
1233 * thread getting in. The channel spin lock in the mailbox framework in pdc_send_data()
1236 tx_desc_req = pdc_desc_count(mssg->spu.src); in pdc_send_data()
1237 rx_desc_req = pdc_desc_count(mssg->spu.dst); in pdc_send_data()
1239 return -ENOSPC; in pdc_send_data()
1242 err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx); in pdc_send_data()
1243 err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst); in pdc_send_data()
1245 /* Create tx descriptors to submit SPU request */ in pdc_send_data()
1246 err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src); in pdc_send_data()
1250 dev_err(&pdcs->pdev->dev, in pdc_send_data()
1258 return pdc_ring_init(chan->con_priv, PDC_RINGSET); in pdc_startup()
1263 struct pdc_state *pdcs = chan->con_priv; in pdc_shutdown()
1268 dev_dbg(&pdcs->pdev->dev, in pdc_shutdown()
1269 "Shutdown mailbox channel for PDC %u", pdcs->pdc_idx); in pdc_shutdown()
1274 * pdc_hw_init() - Use the given initialization parameters to initialize the
1286 pdev = pdcs->pdev; in pdc_hw_init()
1287 dev = &pdev->dev; in pdc_hw_init()
1289 dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx); in pdc_hw_init()
1292 dev_dbg(dev, " - base virtual addr of hw regs %p", in pdc_hw_init()
1293 pdcs->pdc_reg_vbase); in pdc_hw_init()
1296 pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase; in pdc_hw_init()
1297 pdcs->txregs_64 = (struct dma64_regs *) in pdc_hw_init()
1298 (((u8 *)pdcs->pdc_reg_vbase) + in pdc_hw_init()
1300 pdcs->rxregs_64 = (struct dma64_regs *) in pdc_hw_init()
1301 (((u8 *)pdcs->pdc_reg_vbase) + in pdc_hw_init()
1304 pdcs->ntxd = PDC_RING_ENTRIES; in pdc_hw_init()
1305 pdcs->nrxd = PDC_RING_ENTRIES; in pdc_hw_init()
1306 pdcs->ntxpost = PDC_RING_ENTRIES - 1; in pdc_hw_init()
1307 pdcs->nrxpost = PDC_RING_ENTRIES - 1; in pdc_hw_init()
1308 iowrite32(0, &pdcs->regs->intmask); in pdc_hw_init()
1310 dma_reg = &pdcs->regs->dmaregs[ringset]; in pdc_hw_init()
1313 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_hw_init()
1315 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), in pdc_hw_init()
1316 &dma_reg->dmarcv.control); in pdc_hw_init()
1319 iowrite32(0, &dma_reg->dmaxmt.ptr); in pdc_hw_init()
1320 iowrite32(0, &dma_reg->dmarcv.ptr); in pdc_hw_init()
1322 if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN) in pdc_hw_init()
1324 pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET); in pdc_hw_init()
1328 * pdc_hw_disable() - Disable the tx and rx control in the hw.
1336 dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET]; in pdc_hw_disable()
1337 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_hw_disable()
1338 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), in pdc_hw_disable()
1339 &dma_reg->dmarcv.control); in pdc_hw_disable()
1343 * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata
1347 * The metadata is not returned to the mailbox client. So the PDC driver
1351 * -ENOMEM if pool creation fails
1358 pdev = pdcs->pdev; in pdc_rx_buf_pool_create()
1359 dev = &pdev->dev; in pdc_rx_buf_pool_create()
1361 pdcs->pdc_resp_hdr_len = pdcs->rx_status_len; in pdc_rx_buf_pool_create()
1362 if (pdcs->use_bcm_hdr) in pdc_rx_buf_pool_create()
1363 pdcs->pdc_resp_hdr_len += BCM_HDR_LEN; in pdc_rx_buf_pool_create()
1365 pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev, in pdc_rx_buf_pool_create()
1366 pdcs->pdc_resp_hdr_len, in pdc_rx_buf_pool_create()
1368 if (!pdcs->rx_buf_pool) in pdc_rx_buf_pool_create()
1369 return -ENOMEM; in pdc_rx_buf_pool_create()
1375 * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and
1381 * Set the lazy interrupt frame count to generate an interrupt for just one pkt.
1388 struct platform_device *pdev = pdcs->pdev; in pdc_interrupts_init()
1389 struct device *dev = &pdev->dev; in pdc_interrupts_init()
1390 struct device_node *dn = pdev->dev.of_node; in pdc_interrupts_init()
1394 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_interrupts_init()
1396 if (pdcs->hw_type == FA_HW) in pdc_interrupts_init()
1397 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + in pdc_interrupts_init()
1400 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + in pdc_interrupts_init()
1404 pdcs->pdc_irq = irq_of_parse_and_map(dn, 0); in pdc_interrupts_init()
1406 dev_name(dev), pdcs->pdc_irq, pdcs); in pdc_interrupts_init()
1408 err = devm_request_irq(dev, pdcs->pdc_irq, pdc_irq_handler, 0, in pdc_interrupts_init()
1412 pdcs->pdc_irq, err); in pdc_interrupts_init()
1426 * pdc_mb_init() - Initialize the mailbox controller.
1429 * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel
1431 * complete interrupt to determine when a mailbox message has successfully been
1439 struct device *dev = &pdcs->pdev->dev; in pdc_mb_init()
1444 mbc = &pdcs->mbc; in pdc_mb_init()
1445 mbc->dev = dev; in pdc_mb_init()
1446 mbc->ops = &pdc_mbox_chan_ops; in pdc_mb_init()
1447 mbc->num_chans = 1; in pdc_mb_init()
1448 mbc->chans = devm_kcalloc(dev, mbc->num_chans, sizeof(*mbc->chans), in pdc_mb_init()
1450 if (!mbc->chans) in pdc_mb_init()
1451 return -ENOMEM; in pdc_mb_init()
1453 mbc->txdone_irq = false; in pdc_mb_init()
1454 mbc->txdone_poll = true; in pdc_mb_init()
1455 mbc->txpoll_period = 1; in pdc_mb_init()
1456 for (chan_index = 0; chan_index < mbc->num_chans; chan_index++) in pdc_mb_init()
1457 mbc->chans[chan_index].con_priv = pdcs; in pdc_mb_init()
1459 /* Register mailbox controller */ in pdc_mb_init()
1463 "Failed to register PDC mailbox controller. Error %d.", in pdc_mb_init()
1475 {.compatible = "brcm,iproc-pdc-mbox", .data = &pdc_hw},
1476 {.compatible = "brcm,iproc-fa2-mbox", .data = &fa_hw},
1482 * pdc_dt_read() - Read application-specific data from device tree.
1487 * Reads whether transmit and received frames should be preceded by an 8-byte
1491 * -ENODEV if device not available
1495 struct device *dev = &pdev->dev; in pdc_dt_read()
1496 struct device_node *dn = pdev->dev.of_node; in pdc_dt_read()
1501 err = of_property_read_u32(dn, "brcm,rx-status-len", in pdc_dt_read()
1502 &pdcs->rx_status_len); in pdc_dt_read()
1508 pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr"); in pdc_dt_read()
1510 pdcs->hw_type = PDC_HW; in pdc_dt_read()
1514 hw_type = match->data; in pdc_dt_read()
1515 pdcs->hw_type = *hw_type; in pdc_dt_read()
1522 * pdc_probe() - Probe function for PDC driver.
1526 * Allocate and initialize tx and rx DMA rings.
1527 * Initialize a mailbox controller for each PDC.
1535 struct device *dev = &pdev->dev; in pdc_probe()
1542 err = -ENOMEM; in pdc_probe()
1546 pdcs->pdev = pdev; in pdc_probe()
1548 pdcs->pdc_idx = pdcg.num_spu; in pdc_probe()
1557 /* Create DMA pool for tx ring */ in pdc_probe()
1558 pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE, in pdc_probe()
1560 if (!pdcs->ring_pool) { in pdc_probe()
1561 err = -ENOMEM; in pdc_probe()
1569 pdcs->pdc_reg_vbase = devm_platform_get_and_ioremap_resource(pdev, 0, &pdc_regs); in pdc_probe()
1570 if (IS_ERR(pdcs->pdc_reg_vbase)) { in pdc_probe()
1571 err = PTR_ERR(pdcs->pdc_reg_vbase); in pdc_probe()
1575 &pdc_regs->start, &pdc_regs->end); in pdc_probe()
1585 tasklet_setup(&pdcs->rx_tasklet, pdc_tasklet_cb); in pdc_probe()
1591 /* Initialize mailbox controller */ in pdc_probe()
1602 tasklet_kill(&pdcs->rx_tasklet); in pdc_probe()
1603 dma_pool_destroy(pdcs->rx_buf_pool); in pdc_probe()
1606 dma_pool_destroy(pdcs->ring_pool); in pdc_probe()
1618 tasklet_kill(&pdcs->rx_tasklet); in pdc_remove()
1622 dma_pool_destroy(pdcs->rx_buf_pool); in pdc_remove()
1623 dma_pool_destroy(pdcs->ring_pool); in pdc_remove()
1631 .name = "brcm-iproc-pdc-mbox",
1638 MODULE_DESCRIPTION("Broadcom PDC mailbox driver");