drivers/irqchip/irq-sunxi-nmi.c

2  * Allwinner A20/A31 SoCs NMI IRQ chip driver.
11 #define DRV_NAME	"sunxi-nmi"
30  * For deprecated sun6i-a31-sc-nmi compatible.
99 	struct irq_chip_type *ct = gc->chip_types;  in sunxi_sc_nmi_set_type()
101 	u32 ctrl_off = ct->regs.type;  in sunxi_sc_nmi_set_type()
124 			data->irq);  in sunxi_sc_nmi_set_type()
125 		return -EBADR;  in sunxi_sc_nmi_set_type()
131 	for (i = 0; i < gc->num_ct; i++, ct++)  in sunxi_sc_nmi_set_type()
132 		if (ct->type & flow_type)  in sunxi_sc_nmi_set_type()
133 			ctrl_off = ct->regs.type;  in sunxi_sc_nmi_set_type()
158 		return -ENOMEM;  in sunxi_sc_nmi_irq_init()
172 		ret = -EINVAL;  in sunxi_sc_nmi_irq_init()
177 	gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));  in sunxi_sc_nmi_irq_init()
178 	if (IS_ERR(gc->reg_base)) {  in sunxi_sc_nmi_irq_init()
180 		ret = PTR_ERR(gc->reg_base);  in sunxi_sc_nmi_irq_init()
184 	gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;  in sunxi_sc_nmi_irq_init()
185 	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;  in sunxi_sc_nmi_irq_init()
186 	gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;  in sunxi_sc_nmi_irq_init()
187 	gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;  in sunxi_sc_nmi_irq_init()
188 	gc->chip_types[0].chip.irq_set_type	= sunxi_sc_nmi_set_type;  in sunxi_sc_nmi_irq_init()
189 	gc->chip_types[0].chip.flags		= IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED;  in sunxi_sc_nmi_irq_init()
190 	gc->chip_types[0].regs.ack		= reg_offs->pend;  in sunxi_sc_nmi_irq_init()
191 	gc->chip_types[0].regs.mask		= reg_offs->enable;  in sunxi_sc_nmi_irq_init()
192 	gc->chip_types[0].regs.type		= reg_offs->ctrl;  in sunxi_sc_nmi_irq_init()
194 	gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;  in sunxi_sc_nmi_irq_init()
195 	gc->chip_types[1].chip.name		= gc->chip_types[0].chip.name;  in sunxi_sc_nmi_irq_init()
196 	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;  in sunxi_sc_nmi_irq_init()
197 	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;  in sunxi_sc_nmi_irq_init()
198 	gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;  in sunxi_sc_nmi_irq_init()
199 	gc->chip_types[1].chip.irq_set_type	= sunxi_sc_nmi_set_type;  in sunxi_sc_nmi_irq_init()
200 	gc->chip_types[1].regs.ack		= reg_offs->pend;  in sunxi_sc_nmi_irq_init()
201 	gc->chip_types[1].regs.mask		= reg_offs->enable;  in sunxi_sc_nmi_irq_init()
202 	gc->chip_types[1].regs.type		= reg_offs->ctrl;  in sunxi_sc_nmi_irq_init()
203 	gc->chip_types[1].handler		= handle_edge_irq;  in sunxi_sc_nmi_irq_init()
206 	sunxi_sc_nmi_write(gc, reg_offs->enable, 0);  in sunxi_sc_nmi_irq_init()
208 	/* Clear any pending NMI interrupts */  in sunxi_sc_nmi_irq_init()
209 	sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT);  in sunxi_sc_nmi_irq_init()
226 IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init);
233 IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
240 IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);