Lines Matching refs:irq_ic_data
45 static struct sun4i_irq_chip_data *irq_ic_data; variable
56 writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_irq_ack()
66 val = readl(irq_ic_data->irq_base + in sun4i_irq_mask()
67 SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); in sun4i_irq_mask()
69 irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); in sun4i_irq_mask()
79 val = readl(irq_ic_data->irq_base + in sun4i_irq_unmask()
80 SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); in sun4i_irq_unmask()
82 irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); in sun4i_irq_unmask()
110 irq_ic_data->irq_base = of_iomap(node, 0); in sun4i_of_init()
111 if (!irq_ic_data->irq_base) in sun4i_of_init()
116 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0)); in sun4i_of_init()
117 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1)); in sun4i_of_init()
118 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2)); in sun4i_of_init()
121 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0)); in sun4i_of_init()
122 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1)); in sun4i_of_init()
123 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2)); in sun4i_of_init()
126 writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_of_init()
127 writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1)); in sun4i_of_init()
128 writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2)); in sun4i_of_init()
131 writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG); in sun4i_of_init()
134 writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG); in sun4i_of_init()
136 irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32, in sun4i_of_init()
138 if (!irq_ic_data->irq_domain) in sun4i_of_init()
149 irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); in sun4i_ic_of_init()
150 if (!irq_ic_data) in sun4i_ic_of_init()
153 irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; in sun4i_ic_of_init()
154 irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; in sun4i_ic_of_init()
164 irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); in suniv_ic_of_init()
165 if (!irq_ic_data) in suniv_ic_of_init()
168 irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; in suniv_ic_of_init()
169 irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; in suniv_ic_of_init()
191 hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; in sun4i_handle_irq()
193 !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) & in sun4i_handle_irq()
198 generic_handle_domain_irq(irq_ic_data->irq_domain, hwirq); in sun4i_handle_irq()
199 hwirq = readl(irq_ic_data->irq_base + in sun4i_handle_irq()