Lines Matching +full:rzg2l +full:- +full:irqc
1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L IRQC Driver
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
61 * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
71 * struct rzg2l_irqc_priv - IRQ controller private data structure
86 return data->domain->host_data; in irq_data_to_priv()
91 unsigned int hw_irq = hwirq - IRQC_IRQ_START; in rzg2l_clear_irq_int()
95 iscr = readl_relaxed(priv->base + ISCR); in rzg2l_clear_irq_int()
96 iitsr = readl_relaxed(priv->base + IITSR); in rzg2l_clear_irq_int()
99 * ISCR can only be cleared if the type is falling-edge, rising-edge or in rzg2l_clear_irq_int()
100 * falling/rising-edge. in rzg2l_clear_irq_int()
103 writel_relaxed(iscr & ~bit, priv->base + ISCR); in rzg2l_clear_irq_int()
108 readl_relaxed(priv->base + ISCR); in rzg2l_clear_irq_int()
114 u32 bit = BIT(hwirq - IRQC_TINT_START); in rzg2l_clear_tint_int()
117 reg = readl_relaxed(priv->base + TSCR); in rzg2l_clear_tint_int()
119 writel_relaxed(reg & ~bit, priv->base + TSCR); in rzg2l_clear_tint_int()
124 readl_relaxed(priv->base + TSCR); in rzg2l_clear_tint_int()
133 raw_spin_lock(&priv->lock); in rzg2l_irqc_eoi()
138 raw_spin_unlock(&priv->lock); in rzg2l_irqc_eoi()
148 u32 offset = hw_irq - IRQC_TINT_START; in rzg2l_irqc_irq_disable()
153 raw_spin_lock(&priv->lock); in rzg2l_irqc_irq_disable()
154 reg = readl_relaxed(priv->base + TSSR(tssr_index)); in rzg2l_irqc_irq_disable()
156 writel_relaxed(reg, priv->base + TSSR(tssr_index)); in rzg2l_irqc_irq_disable()
157 raw_spin_unlock(&priv->lock); in rzg2l_irqc_irq_disable()
168 u32 offset = hw_irq - IRQC_TINT_START; in rzg2l_irqc_irq_enable()
173 raw_spin_lock(&priv->lock); in rzg2l_irqc_irq_enable()
174 reg = readl_relaxed(priv->base + TSSR(tssr_index)); in rzg2l_irqc_irq_enable()
176 writel_relaxed(reg, priv->base + TSSR(tssr_index)); in rzg2l_irqc_irq_enable()
177 raw_spin_unlock(&priv->lock); in rzg2l_irqc_irq_enable()
186 u32 iitseln = hwirq - IRQC_IRQ_START; in rzg2l_irq_set_type()
211 return -EINVAL; in rzg2l_irq_set_type()
214 raw_spin_lock(&priv->lock); in rzg2l_irq_set_type()
215 tmp = readl_relaxed(priv->base + IITSR); in rzg2l_irq_set_type()
220 writel_relaxed(tmp, priv->base + IITSR); in rzg2l_irq_set_type()
221 raw_spin_unlock(&priv->lock); in rzg2l_irq_set_type()
236 writel_relaxed(reg, priv->base + TSSR(tssr_index)); in rzg2l_disable_tint_and_set_tint_source()
245 u32 titseln = hwirq - IRQC_TINT_START; in rzg2l_tint_set_edge()
261 return -EINVAL; in rzg2l_tint_set_edge()
266 titseln -= TITSR0_MAX_INT; in rzg2l_tint_set_edge()
270 raw_spin_lock(&priv->lock); in rzg2l_tint_set_edge()
271 tssr = readl_relaxed(priv->base + TSSR(tssr_index)); in rzg2l_tint_set_edge()
273 reg = readl_relaxed(priv->base + TITSR(index)); in rzg2l_tint_set_edge()
276 writel_relaxed(reg, priv->base + TITSR(index)); in rzg2l_tint_set_edge()
278 writel_relaxed(tssr, priv->base + TSSR(tssr_index)); in rzg2l_tint_set_edge()
279 raw_spin_unlock(&priv->lock); in rzg2l_tint_set_edge()
287 int ret = -EINVAL; in rzg2l_irqc_set_type()
301 struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; in rzg2l_irqc_irq_suspend()
302 void __iomem *base = rzg2l_irqc_data->base; in rzg2l_irqc_irq_suspend()
304 cache->iitsr = readl_relaxed(base + IITSR); in rzg2l_irqc_irq_suspend()
306 cache->titsr[i] = readl_relaxed(base + TITSR(i)); in rzg2l_irqc_irq_suspend()
313 struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; in rzg2l_irqc_irq_resume()
314 void __iomem *base = rzg2l_irqc_data->base; in rzg2l_irqc_irq_resume()
322 writel_relaxed(cache->titsr[i], base + TITSR(i)); in rzg2l_irqc_irq_resume()
323 writel_relaxed(cache->iitsr, base + IITSR); in rzg2l_irqc_irq_resume()
332 .name = "rzg2l-irqc",
350 struct rzg2l_irqc_priv *priv = domain->host_data; in rzg2l_irqc_alloc()
361 * For TINT interrupts ie where pinctrl driver is child of irqc domain in rzg2l_irqc_alloc()
362 * the hwirq and TINT are encoded in fwspec->param[0]. in rzg2l_irqc_alloc()
363 * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT in rzg2l_irqc_alloc()
364 * from 16-31 bits. TINT from the pinctrl driver needs to be programmed in rzg2l_irqc_alloc()
365 * in IRQC registers to enable a given gpio pin as interrupt. in rzg2l_irqc_alloc()
372 return -EINVAL; in rzg2l_irqc_alloc()
375 if (hwirq > (IRQC_NUM_IRQ - 1)) in rzg2l_irqc_alloc()
376 return -EINVAL; in rzg2l_irqc_alloc()
383 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]); in rzg2l_irqc_alloc()
404 &priv->fwspec[i]); in rzg2l_irqc_parse_interrupts()
413 struct device *dev __free(put_device) = pdev ? &pdev->dev : NULL; in rzg2l_irqc_init()
419 return -ENODEV; in rzg2l_irqc_init()
423 dev_err(&pdev->dev, "cannot find parent domain\n"); in rzg2l_irqc_init()
424 return -ENODEV; in rzg2l_irqc_init()
427 rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL); in rzg2l_irqc_init()
429 return -ENOMEM; in rzg2l_irqc_init()
431 rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); in rzg2l_irqc_init()
432 if (IS_ERR(rzg2l_irqc_data->base)) in rzg2l_irqc_init()
433 return PTR_ERR(rzg2l_irqc_data->base); in rzg2l_irqc_init()
437 dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); in rzg2l_irqc_init()
441 resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); in rzg2l_irqc_init()
447 dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); in rzg2l_irqc_init()
451 pm_runtime_enable(&pdev->dev); in rzg2l_irqc_init()
452 ret = pm_runtime_resume_and_get(&pdev->dev); in rzg2l_irqc_init()
454 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); in rzg2l_irqc_init()
458 raw_spin_lock_init(&rzg2l_irqc_data->lock); in rzg2l_irqc_init()
464 dev_err(&pdev->dev, "failed to add irq domain\n"); in rzg2l_irqc_init()
465 ret = -ENOMEM; in rzg2l_irqc_init()
485 pm_runtime_put(&pdev->dev); in rzg2l_irqc_init()
487 pm_runtime_disable(&pdev->dev); in rzg2l_irqc_init()
493 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
495 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
496 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");