Lines Matching refs:p
81 struct chip_props *p = d->host_data; in ocelot_irq_unmask() local
87 val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) | in ocelot_irq_unmask()
88 irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1)); in ocelot_irq_unmask()
90 irq_reg_writel(gc, mask, p->reg_off_sticky); in ocelot_irq_unmask()
93 irq_reg_writel(gc, mask, p->reg_off_ena_set); in ocelot_irq_unmask()
101 struct chip_props *p = d->host_data; in ocelot_irq_handler() local
103 u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0)); in ocelot_irq_handler()
119 struct chip_props *p) in vcoreiii_irq_init() argument
129 domain = irq_domain_add_linear(node, p->n_irq, in vcoreiii_irq_init()
136 ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1, in vcoreiii_irq_init()
153 gc->chip_types[0].regs.ack = p->reg_off_sticky; in vcoreiii_irq_init()
154 if (p->flags & FLAGS_HAS_TRIGGER) { in vcoreiii_irq_init()
155 gc->chip_types[0].regs.mask = p->reg_off_ena_clr; in vcoreiii_irq_init()
159 gc->chip_types[0].regs.enable = p->reg_off_ena_set; in vcoreiii_irq_init()
160 gc->chip_types[0].regs.disable = p->reg_off_ena_clr; in vcoreiii_irq_init()
166 irq_reg_writel(gc, 0, p->reg_off_ena); in vcoreiii_irq_init()
167 irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky); in vcoreiii_irq_init()
170 if (p->flags & FLAGS_NEED_INIT_ENABLE) in vcoreiii_irq_init()
171 irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0); in vcoreiii_irq_init()
173 domain->host_data = p; in vcoreiii_irq_init()