1 // SPDX-License-Identifier: GPL-2.0-only
3  * Freescale MU used as MSI controller
10  * Based on drivers/mailbox/imx-mailbox.c
20 #include <linux/msi.h>
50 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
51 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
73 	iowrite32(val, msi_data->regs + offs);  in imx_mu_write()
78 	return ioread32(msi_data->regs + offs);  in imx_mu_read()
86 	raw_spin_lock_irqsave(&msi_data->lock, flags);  in imx_mu_xcr_rmw()
87 	val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]);  in imx_mu_xcr_rmw()
90 	imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]);  in imx_mu_xcr_rmw()
91 	raw_spin_unlock_irqrestore(&msi_data->lock, flags);  in imx_mu_xcr_rmw()
100 	imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq));  in imx_mu_msi_parent_mask_irq()
107 	imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0);  in imx_mu_msi_parent_unmask_irq()
114 	imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4);  in imx_mu_msi_parent_ack_irq()
118 	.name = "MU-MSI",
135 	u64 addr = msi_data->msiir_addr + 4 * data->hwirq;  in imx_mu_msi_parent_compose_msg()
137 	msg->address_hi = upper_32_bits(addr);  in imx_mu_msi_parent_compose_msg()
138 	msg->address_lo = lower_32_bits(addr);  in imx_mu_msi_parent_compose_msg()
139 	msg->data = data->hwirq;  in imx_mu_msi_parent_compose_msg()
145 	return -EINVAL;  in imx_mu_msi_parent_set_affinity()
149 	.name		= "MU",
162 	struct imx_mu_msi *msi_data = domain->host_data;  in imx_mu_msi_domain_irq_alloc()
168 	raw_spin_lock_irqsave(&msi_data->lock, flags);  in imx_mu_msi_domain_irq_alloc()
169 	pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS);  in imx_mu_msi_domain_irq_alloc()
171 		__set_bit(pos, &msi_data->used);  in imx_mu_msi_domain_irq_alloc()
173 		err = -ENOSPC;  in imx_mu_msi_domain_irq_alloc()
174 	raw_spin_unlock_irqrestore(&msi_data->lock, flags);  in imx_mu_msi_domain_irq_alloc()
192 	raw_spin_lock_irqsave(&msi_data->lock, flags);  in imx_mu_msi_domain_irq_free()
193 	__clear_bit(d->hwirq, &msi_data->used);  in imx_mu_msi_domain_irq_free()
194 	raw_spin_unlock_irqrestore(&msi_data->lock, flags);  in imx_mu_msi_domain_irq_free()
209 	status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]);  in imx_mu_msi_irq_handler()
214 			generic_handle_domain_irq(msi_data->msi_domain, i);  in imx_mu_msi_irq_handler()
224 	/* Initialize MSI domain parent */  in imx_mu_msi_domains_init()
231 		return -ENOMEM;  in imx_mu_msi_domains_init()
236 	msi_data->msi_domain = platform_msi_create_irq_domain(fwnodes,  in imx_mu_msi_domains_init()
240 	if (!msi_data->msi_domain) {  in imx_mu_msi_domains_init()
241 		dev_err(dev, "failed to create MSI domain\n");  in imx_mu_msi_domains_init()
243 		return -ENOMEM;  in imx_mu_msi_domains_init()
246 	irq_domain_set_pm_device(msi_data->msi_domain, dev);  in imx_mu_msi_domains_init()
251 /* Register offset of different version MU IP */
321 	dev = &pdev->dev;  in imx_mu_of_init()
323 	msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);  in imx_mu_of_init()
325 		return -ENOMEM;  in imx_mu_of_init()
327 	msi_data->cfg = cfg;  in imx_mu_of_init()
329 	msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor-a-side");  in imx_mu_of_init()
330 	if (IS_ERR(msi_data->regs)) {  in imx_mu_of_init()
331 		dev_err(&pdev->dev, "failed to initialize 'regs'\n");  in imx_mu_of_init()
332 		return PTR_ERR(msi_data->regs);  in imx_mu_of_init()
335 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor-b-side");  in imx_mu_of_init()
337 		return -EIO;  in imx_mu_of_init()
339 	msi_data->msiir_addr = res->start + msi_data->cfg->xTR;  in imx_mu_of_init()
347 	msi_data->clk = devm_clk_get(dev, NULL);  in imx_mu_of_init()
348 	if (IS_ERR(msi_data->clk))  in imx_mu_of_init()
349 		return PTR_ERR(msi_data->clk);  in imx_mu_of_init()
351 	pd_a = dev_pm_domain_attach_by_name(dev, "processor-a-side");  in imx_mu_of_init()
355 	pd_b = dev_pm_domain_attach_by_name(dev, "processor-b-side");  in imx_mu_of_init()
365 		dev_err(dev, "Failed to add device_link to mu a.\n");  in imx_mu_of_init()
376 		dev_err(dev, "Failed to add device_link to mu a.\n");  in imx_mu_of_init()
397 	return -EINVAL;  in imx_mu_of_init()
404 	clk_disable_unprepare(priv->clk);  in imx_mu_runtime_suspend()
414 	ret = clk_prepare_enable(priv->clk);  in imx_mu_runtime_resume()
445 IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init)
446 IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init)
447 IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init)
452 MODULE_DESCRIPTION("Freescale MU MSI controller driver");