1 // SPDX-License-Identifier: GPL-2.0-only
33 	return cd->gpc_base + cd->cpu2wakeup + i * 4;  in gpcv2_idx_to_reg()
48 		cd->saved_irq_mask[i] = readl_relaxed(reg);  in gpcv2_wakeup_source_save()
49 		writel_relaxed(cd->wakeup_sources[i], reg);  in gpcv2_wakeup_source_save()
65 		writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));  in gpcv2_wakeup_source_restore()
75 	struct gpcv2_irqchip_data *cd = d->chip_data;  in imx_gpcv2_irq_set_wake()
76 	unsigned int idx = d->hwirq / 32;  in imx_gpcv2_irq_set_wake()
80 	raw_spin_lock_irqsave(&cd->rlock, flags);  in imx_gpcv2_irq_set_wake()
81 	mask = BIT(d->hwirq % 32);  in imx_gpcv2_irq_set_wake()
82 	val = cd->wakeup_sources[idx];  in imx_gpcv2_irq_set_wake()
84 	cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);  in imx_gpcv2_irq_set_wake()
85 	raw_spin_unlock_irqrestore(&cd->rlock, flags);  in imx_gpcv2_irq_set_wake()
89 	 * wake-up facility...  in imx_gpcv2_irq_set_wake()
97 	struct gpcv2_irqchip_data *cd = d->chip_data;  in imx_gpcv2_irq_unmask()
101 	raw_spin_lock(&cd->rlock);  in imx_gpcv2_irq_unmask()
102 	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);  in imx_gpcv2_irq_unmask()
104 	val &= ~BIT(d->hwirq % 32);  in imx_gpcv2_irq_unmask()
106 	raw_spin_unlock(&cd->rlock);  in imx_gpcv2_irq_unmask()
113 	struct gpcv2_irqchip_data *cd = d->chip_data;  in imx_gpcv2_irq_mask()
117 	raw_spin_lock(&cd->rlock);  in imx_gpcv2_irq_mask()
118 	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);  in imx_gpcv2_irq_mask()
120 	val |= BIT(d->hwirq % 32);  in imx_gpcv2_irq_mask()
122 	raw_spin_unlock(&cd->rlock);  in imx_gpcv2_irq_mask()
145 	if (is_of_node(fwspec->fwnode)) {  in imx_gpcv2_domain_translate()
146 		if (fwspec->param_count != 3)  in imx_gpcv2_domain_translate()
147 			return -EINVAL;  in imx_gpcv2_domain_translate()
150 		if (fwspec->param[0] != 0)  in imx_gpcv2_domain_translate()
151 			return -EINVAL;  in imx_gpcv2_domain_translate()
153 		*hwirq = fwspec->param[1];  in imx_gpcv2_domain_translate()
154 		*type = fwspec->param[2];  in imx_gpcv2_domain_translate()
158 	return -EINVAL;  in imx_gpcv2_domain_translate()
177 		return -EINVAL;  in imx_gpcv2_domain_alloc()
181 				&gpcv2_irqchip_data_chip, domain->host_data);  in imx_gpcv2_domain_alloc()
185 	parent_fwspec.fwnode = domain->parent->fwnode;  in imx_gpcv2_domain_alloc()
197 	{ .compatible = "fsl,imx7d-gpc",  .data = (const void *) 2 },
198 	{ .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
213 		return -ENODEV;  in imx_gpcv2_irqchip_init()
219 		return -ENODEV;  in imx_gpcv2_irqchip_init()
222 	core_num = (unsigned long)id->data;  in imx_gpcv2_irqchip_init()
227 		return -ENXIO;  in imx_gpcv2_irqchip_init()
232 		return -ENOMEM;  in imx_gpcv2_irqchip_init()
234 	raw_spin_lock_init(&cd->rlock);  in imx_gpcv2_irqchip_init()
236 	cd->gpc_base = of_iomap(node, 0);  in imx_gpcv2_irqchip_init()
237 	if (!cd->gpc_base) {  in imx_gpcv2_irqchip_init()
238 		pr_err("%pOF: unable to map gpc registers\n", node);  in imx_gpcv2_irqchip_init()
240 		return -ENOMEM;  in imx_gpcv2_irqchip_init()
246 		iounmap(cd->gpc_base);  in imx_gpcv2_irqchip_init()
248 		return -ENOMEM;  in imx_gpcv2_irqchip_init()
254 		void __iomem *reg = cd->gpc_base + i * 4;  in imx_gpcv2_irqchip_init()
265 		cd->wakeup_sources[i] = ~0;  in imx_gpcv2_irqchip_init()
268 	/* Let CORE0 as the default CPU to wake up by GPC */  in imx_gpcv2_irqchip_init()
269 	cd->cpu2wakeup = GPC_IMR1_CORE0;  in imx_gpcv2_irqchip_init()
276 	writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);  in imx_gpcv2_irqchip_init()
283 	 * later the GPC power domain driver will not be skipped.  in imx_gpcv2_irqchip_init()
286 	fwnode_dev_initialized(domain->fwnode, false);  in imx_gpcv2_irqchip_init()
290 IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
291 IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);