iommu/intel/iommu.h

653 struct intel_iommu {  struct
654 	void __iomem	*reg; /* Pointer to hardware regs, virtual addr */
655 	u64 		reg_phys; /* physical address of hw register set */
656 	u64		reg_size; /* size of hw register set */
657 	u64		cap;
658 	u64		ecap;
659 	u64		vccap;
660 	u64		ecmdcap[DMA_MAX_NUM_ECMDCAP];
661 	u32		gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
662 	raw_spinlock_t	register_lock; /* protect register handling */
663 	int		seq_id;	/* sequence id of the iommu */
664 	int		agaw; /* agaw of this iommu */
665 	int		msagaw; /* max sagaw of this iommu */
666 	unsigned int	irq, pr_irq, perf_irq;
667 	u16		segment;     /* PCI segment# */
668 	unsigned char 	name[13];    /* Device Name */
671 	unsigned long 	*domain_ids; /* bitmap of domains */
672 	unsigned long	*copied_tables; /* bitmap of copied tables */
673 	spinlock_t	lock; /* protect context, domain ids */
674 	struct root_entry *root_entry; /* virtual address */
676 	struct iommu_flush flush;
679 	struct page_req_dsc *prq;
680 	unsigned char prq_name[16];    /* Name for PRQ interrupt */
681 	unsigned long prq_seq_number;
682 	struct completion prq_complete;
684 	struct iopf_queue *iopf_queue;
685 	unsigned char iopfq_name[16];
686 	struct q_inval  *qi;            /* Queued invalidation info */
687 	u32 iommu_state[MAX_SR_DMAR_REGS]; /* Store iommu states between suspend and resume.*/
690 	struct ir_table *ir_table;	/* Interrupt remapping info */
691 	struct irq_domain *ir_domain;
693 	struct iommu_device iommu;  /* IOMMU core code handle */
694 	int		node;
695 	u32		flags;      /* Software defined flags */
719 	struct intel_iommu *iommu; /* IOMMU used by this device */  argument